User's Manual

UniStone
General Device Overview
Product Overview 10 T3130-8XV10PO5-7600, 2007-01-31
.
Pin No. Symbol Input/
Output
Supply
voltage
During
Reset
After
Reset
Function
A2 P1.6 I/O/OD Internal1 Z Z Port 1.6
A3 RESET# AI Internal1 Input Input Hardware Reset
A8 P1.5/
CLK32
I/O/OD Internal1 Input Input Port 1.5 or
LPM clock input (e.g.
32.768kHz)
B1 P1.7/
WAKEUP_BT
I/O/OD Internal1 PD/
Input
PD/
Input
Port 1.7 or
Bluetooth wake-up signal
B2 P1.8/
WAKEUP_HOST
I/O/OD Internal1 PD PD Port 1.8 or
Host wake-up signal
B3 P1.0/
TMS
I/O/OD Internal2 PU
1)
PU
1)
Port 1.0 or
JTAG interface
B4 P1.4/
RTCK
I/O/OD Internal2 Z Z Port 1.4 or
JTAG interface
B5 ONOFF I - - Turns off module completely
B9 SLEEPX I/O VDDUART PD H Sleep indication signal
C2 P0.9 I/O/OD Internal2 Z Z Port 0.9
C3 JTAG# I Internal2 PU PU Mode selection Port 1:
0: JTAG
1: Port
C4 TRST# I Internal2 PD PD JTAG interface
D1 P0.10 I/O/OD Internal2 Z Z Port 0.10
D2 P0.8 I/O/OD Internal2 PD PD Port 0.8
D3 P1.1/
TCK
I/O/OD Internal2 PU
1)
PU
1)
Port 1.1 or
JTAG interface
D4 P0.3/
PCMOUT
I/O/OD VDDPCM Conf.
PD def.
Conf.
PD def.
Port 0.3 or
PCM data out
D5 P0.2/
PCMIN
I/O/OD VDDPCM Z Z Port 0.2 or
PCM data in
D9 ANTENNA AI/AO inactive inactive RF input/output single ended
E1 P0.12/
SDA0
I/O/OD Internal2 PU PU Port 0.12 or
I2C data signal
E2 P0.13/
SCL0
I/O/OD Internal2 PU PU Port 0.13 or
I2C clock signal
E3 P1.3/
TDO/
SLOT_STATE
I/O/OD Internal2 Z Z Port 1.3 or
JTAG interface or
WLAN coexistence interface
E4 P0.0/
PCMFR1
I/O/OD VDDPCM PD PD Port 0.0 or
PCM frame signal 1
E5 P0.1/
PCMCLK
I/O/OD VDDPCM PD PD Port 0.1 or
PCM clock