P rod uc t O v erv i ew T3130-8XV10PO5-7600 Jan 2007 PBA 31308 Bluetooth QD ID : B012097/B012098 UniStone BlueMoon Universal Platform N e v e r s t o p t h i n k i n g .
Edition 2007-01-31 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2007. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.
For questions on technology, delivery and prices, please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.
UniStone PBA 31308 Revision History: 2007-01-31 T3130-8XV10PO5-7600 Previous Version: Section Subjects (major changes since last revision) Product Overview 4 T3130-8XV10PO5-7600, 2007-01-31
UniStone 1 1.1 1.2 1.3 1.4 1.5 1.6 General Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Description . . . . . . . . . . . . . .
UniStone 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.4 6.4.1 6.5 6.5.1 6.5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Driver and Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pull-ups and Pull-downs . . . . . . . . . .
UniStone General Device Overview 1 General Device Overview 1.1 Features General • • • • • • • • • Complete Bluetooth 2.0 + EDR solution Ultra low power design in 0.13 µm CMOS Temperature range from -40°C to 85°C Integrates ARM7TDMI, RAM and patchable ROM On-module voltage regulators. External supply 2.9-4.1V On-module EEPROM with configureable data Reference clock included Low power clock from internal oscillator or external low power clock (e.g. 32.
UniStone General Device Overview 1.2 Block Diagram UniStone EEPROM VDD_PCM I2 C VDD_UART UART - HCI PMB8753 BlueMoon UniCellular PCM1 Vsupply Filter Voltage Regulator Crystal 26 MHz Low Power Clock (Optional) 32.768 kHz Figure 1-1 Balun Simplified block diagram of UniStone.
UniStone General Device Overview 1.3 Pin Configuration LGA 11,6 0,6 1,0 1,2 1,0 1,35 F1 F2 F3 F4 F5 F6 F7 F8 F9 E1 E2 E3 E4 E5 E6 E7 E8 E9 D1 D2 D3 D4 D5 D6 D7 D8 D9 C1 C2 C3 C4 C5 C6 C7 C8 C9 B1 B2 B3 B4 B5 B6 B7 B8 B9 A1 A2 A3 A4 A5 A6 A7 A8 A9 1,2 8,7 1,35 0,6 Figure 1-2 1.4 Pin Configuration for UniStone in Top View (footprint) Pin Description The non-shaded cells indicate pins that will be fixed for the product lifetime.
UniStone General Device Overview . Pin No. Symbol Input/ Output Supply voltage During Reset After Reset Function A2 P1.6 I/O/OD Internal1 Z Z Port 1.6 A3 RESET# AI Internal1 Input Input Hardware Reset A8 P1.5/ CLK32 I/O/OD Internal1 Input Input Port 1.5 or LPM clock input (e.g. 32.768kHz) B1 P1.7/ WAKEUP_BT I/O/OD Internal1 PD/ Input PD/ Input Port 1.7 or Bluetooth wake-up signal B2 P1.8/ I/O/OD WAKEUP_HOST Internal1 PD PD Port 1.8 or Host wake-up signal B3 P1.
UniStone General Device Overview Pin No. Symbol Input/ Output Supply voltage During Reset After Reset Function E6 P0.5/ UARTRXD I/O/OD VDDUART Z Z Port 0.5 or UART receive data F2 P1.2/ TDI/ RF_ACTIVE I/O/OD Internal2 PU1) PU1) Port 1.2 or JTAG interface or WLAN coexistence interface F3 P0.11/ TX_CONF I/O/OD Internal2 Z Z Port 0.11or WLAN coexistence interface F4 P0.14/ TX_CONF I/O VDDUART Z Z Port 0.14 or WLAN coexistence interface F5 P0.
UniStone General Device Overview 1.5 System Integration UART UARTRTS UARTTXD UARTRXD UARTCTS PCM / I2S UniStone is optimized for a low bill of material (BOM) and a small PCB size. Figure 1-3 shows a typical application example.
UniStone General Device Overview If a WLAN subsystem is collocated with UniStone the WLAN coexistence interface should be used to enhance Bluetooth and WLAN performance. To coexist with external WLAN devices UniStone supports adaptive frequency hopping. 1.6 FW version UniStone is available in different versions. Please check corresponding release documents for latest information.
UniStone Basic Operating Information 2 Basic Operating Information 2.1 Power Supply BlueMoon UniCellular is supplied from a single supply voltage VSUPPLY. This supply voltage must always be present. The Bluemoon UniCellular chip is supplied from an internally generated 2.5 V supply voltage. This voltage can be accessed from the VREG pin. This voltage may not be used for supplying other components in the host system but can be used for referencing the host interfaces.
UniStone Interfaces 3 Interfaces 3.1 HCI / UART Interface The HCI/UART interface is the main communication interface between the host and UniStone. The standard HCI commands are supported together with an Infineon specific set of commands called HCI+. The interface consists of four UART signals and two wake-up signals as shown in Figure 3-1. Depending on which HCI transport layer that is used, some or all of the signals are needed.
UniStone Interfaces 3.1.2.1 Baud Rates The supported baud rates are listed in Table 3-1 together with the small deviation error that results from the internal clock generation. The default baud rate is 115200 Baud. Table 3-1 UART Baud Rates Wanted Baud Rate Real Baud Rate Deviation Error (%) 9600 9615 0.16 19200 19230 0.16 Product Overview 38400 38461 0.16 57600 57522 -0.14 115200 115044 -0.14 230400 230088 -0.14 460800 464285 0.76 921600 928571 0.76 1843200 1857142 0.
UniStone Interfaces 3.2 PCM Interface The PCM interface is used to exchange synchronous data (usually audio) between UniStone and the host as well as to connect e.g. an external audio codec or an external DSP to UniStone. It can be configured as an industry standard PCM interface supporting long and short frame synchronization, as an I2S interface1) or as an IOM-2 interface in terminal mode with reduced capabilities.
UniStone Interfaces 3.2.
UniStone Interfaces 3.3 WLAN Coexistence Interface UniStone has a WLAN coexistence interface that is based on the IEEE 802.15.2 Packet Traffic Arbitration (PTA) scheme1). The interface prevents interference between collocated WLAN and Bluetooth devices by not letting the two devices transmit and/or receive at the same time. WLAN packets and Bluetooth packets are assigned priorities, and a control unit decides on a per-packet basis which of the devices that should be allowed to operate.
UniStone General Device Capabilities 4 General Device Capabilities 4.1 HCI+ and Bluetooth Device Data (BD_DATA) In addition to the standard Bluetooth HCI commands and events, UniStone supports a set of Infineon specific commands and events called HCI+. All Infineon specific features are accessed using HCI+. All configuration information that is critical for correct operation of UniStone is called Bluetooth Device Data (BD_DATA).
UniStone General Device Capabilities combination of code and data. Please consult manufacturer for latest information of available patches.
UniStone Bluetooth Capabilities 5 Bluetooth Capabilities 5.1 Supported Features UniStone supports all features in the Bluetooth 2.
UniStone Bluetooth Capabilities Park State, or has any synchronous logical transports, a role switch will not be performed. 5.2.1.3 Dynamic Polling Strategy In addition to the regular polling scheme, UniStone dynamically assigns unused slots to links where data is exchanged. This adapts very well to bursty traffic and improves throughput and latency on the links. 5.2.1.4 Adaptive Frequency Hopping (AFH) UniStone supports adaptive frequency hopping according to the Bluetooth 2.0 + EDR specification.
UniStone Bluetooth Capabilities 5.2.2.1 Interface The interface for synchronous data is either the HCI transport layer or the dedicated PCM/I2S interface. The choice of interface for a synchronous connection is done with the HCI+ command Infineon_Config_Synchronous_Interface and must be done before the connection is established. The default interface is configurable via the bit Default_ SCO_interface in the BD_DATA parameter BB_Conf. All details about the PCM/I2S interface are described in Section 3.2.
UniStone Bluetooth Capabilities • Fine tuning can be used on the power steps. The following BD_DATA parameters are used for configuration: RF_Psel_D, RF_Psel_Conf, RF_Conf, TX_Power_Ref#. 5.2.3.3 Ultra Low Transmit Power For high security devices the output power can be reduced to a value that reduces the communication range to a few inches. This mode is enabled with the HCI+ command Infineon_TX_Power_Config.
UniStone Electrical Characteristics 6 Electrical Characteristics 6.1 Absolute Maximum Ratings Table 6-1 Absolute Maximum Ratings Parameter Limit Values Unit Notes 125 oC - -0.3 6.0 V - VDDUART supply voltage -0.9 4.0 V - VDDPCM supply voltage -0.9 4.0 V - VREG -0.3 4.0 V VSUPPLY > 4 V VREG -0.3 VSUPPLY V VSUPPLY < 4 V ONOFF -0.3 VSUPPLY+0.3 V - Input voltage range -0.9 4.0 - Output voltage range -0.
UniStone Electrical Characteristics 6.2 Operating Conditions Table 6-2 Operating Conditions Parameter Limit Values Unit Notes 85 oC - 2.9 4.1 V VDDUART 1.35 3.6 V VDDPCM 1.35 3.
UniStone Electrical Characteristics 6.3 DC Characteristics 6.3.1 Pad Driver and Input Stages Table 6-3 Internal1 (1.5 V) supplied Pins (see Chapter 1.4) Parameter Condition Limit Values Min Unit Typ Max Input low voltage - -0.3 0.27 V Input high voltage - 1.15 3.6 V Output low voltage IOL=1mA 0.25 V Output high voltage IOH=-1mA, 1 mA 10 pF 1 µA 1.1 V Continuous Load1) Pin Capacitance Magnitude Pin Leakage 1) input and output drivers disabled 0.
UniStone Electrical Characteristics Table 6-5 VDDUART supplied Pins (see Chapter 1.4) Parameter Condition Limit Values Unit Min Input low voltage Input high voltage Typ Max -0.3 0.2*VDDUART V P0.5/UARTRXD 0.7*VDDUART VDDUART+0.3 V -Other pins 0.7*VDDUART 3.6 V Output low voltage IOL=5mA VDDUART=2.5V 0.25 V Output low voltage IOL=2mA VDDUART=2.5V 0.15 V Output high voltage IOH=-5mA, VDDUART=2.5V VDDUART-0.25 V Output high voltage IOH=-2mA, VDDUART=2.5V VDDUART-0.
UniStone Electrical Characteristics Table 6-6 VDDPCM supplied Pins (see Chapter 1.4) Parameter Condition Limit Values Min Unit Typ Max Input low voltage -0.3 0.2*VDDPCM V Input high voltage 0.7*VDDPCM 3.6 V Output low voltage IOL=5mA VDDPCM=2.5V 0.25 V Output low voltage IOL=2mA VDDPCM=2.5V 0.15 V Output high voltage IOH=-5mA, VDDPCM=2.5V VDDPCM-0.25 V Output high voltage IOH=-2mA, VDDPCM=2.5V VDDPCM-0.
UniStone Electrical Characteristics 6.3.2 Pull-ups and Pull-downs Table 6-8 Pull-up and pull-down currents Pin Pull Up Current Pull Down Current Unit Conditions Min Typ Max Min Typ Max P0.12/SDA0, P0.13/SCL0 260 740 1300 N/A N/A N/A µA TRST#, JTAG#, P0.0/PCMFR1, P0.1/PCMCLK, P0.2/PCMIN, P0.3/PCMOUT 22 350 150 380 µA P0.4/UARTTXD, P0.5/UARTRXD, P0.6/UARTRTS, P0.7/UARTCTS, P0.10/PSEL1, P0.8/PAON, P0.9/PSEL0, P0.11/RXON, P0.14/TX_CONF, P0.15/SLEEPX 4.2 24 130 P1.0/TMS, 1.1 6.0 P1.
UniStone Electrical Characteristics System Power Consumption Table 6-9 Current Consumption In Different Operating Modes This table shows the Vsupply current consumption. All I/O current is neglected since they depend mainly on the external load. T=25°C, Output Power=0dBm, Parameters Min Typ Max Unit Comment Ultra Low Power Mode 170 µA Page & Inquiry Scan (1.28s) 1.1 mA Sniff (1.28s) 0.35 mA ACL (Transmit DH1) 38 mA Basic Rate, 179.2 kb/s1) ACL (Receive DH1) 35 mA Basic Rate, 179.
UniStone Electrical Characteristics 6.4 AC Characteristics 6.4.1 Characteristics of 32.768 kHz Clock Signal The 32.768 kHz clock signal applied to CLK32 must be a rectangular waveform with a duty cycle of between 10-90%. The frequency accuracy must be better than 250 ppm. The rise and fall time of the signal must be less than 10 µs. 6.5 RF Part 6.5.1 Characteristics RF Part The characteristics involve the spread of values to be within the specific temperature range.
UniStone Electrical Characteristics Table 6-11 BDR - Transmitter Part Parameters Min Typ Initial carrier frequency tolerance |foffset| Max Unit 75 kHz Carrier frequency drift (one slot) |fdrift| 10 25 kHz Carrier frequency drift (three slots) |fdrift| 10 40 kHz Carrier frequency drift (five slots) |fdrift| 10 40 kHz Carrier frequency driftrate (one slot) |fdriftrate| 5 20 kHz/ 50µs Carrier frequency driftrate (three slots) |fdriftrate| 5 20 kHz/ 50µs Carrier frequency driftrate
UniStone Electrical Characteristics Table 6-12 BDR - Receiver Part Parameters Min Unit Conditions Blocking performance 30MHz-2GHz 10 dBm some spurious responses, but according to BT-specification Blocking performance 2GHz-2.4GHz -27 dBm Blocking performance 2.5GHz-3GHz -27 dBm Blocking performance 3GHz-12.
UniStone Electrical Characteristics Table 6-13 EDR - Transmitter Part Parameters Max Unit Conditions 2nd adjacent channel power -20 dBm Carrier power measured at basic rate. ≥3rd adjacent channel power -40 dBm Carrier power measured at basic rate.
UniStone Electrical Characteristics Table 6-14 EDR - Receiver Part Parameters Typ Max Unit 8DPSK - C/I-performance: -2nd adjacent channel (image) -25 0 dB 8DPSK - C/I-performance: -1st adjacent channel -5 5 dB 8DPSK - C/I-performance: co.
UniStone Package Information 7 Package Information 7.1 Package marking Date code FCC ID 7.2 PBA 31308 V1.01 G0644 5N605001 FCC ID: Q2331308 Version Machine readable 2D date code Production Package All dimensions are in mm. Tolerances on all outer dimensions, height, width and length, are +/- 0.2 mm.
UniStone Package Information 7.2.1 Pin mark Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 7-1. Diameter of pin 1 mark on the shield is 0.40 mm. Figure 7-1 Topview and bottom view PBA 31308 V1.
UniStone Acronyms & Abbreviations 8 Acronyms & Abbreviations Acronym or abbreviation Writing out in full ACK Acknowledgement ACL Asynchronous Connection-oriented (logical transport) AFH Adaptive Frequency Hopping AHS Adaptive Hop Sequence ARQ Automatic Repeat reQuest b bit/bits (e.g. kb/s) B Byte/Bytes (e.g.
UniStone Acronyms & Abbreviations Acronym or abbreviation Writing out in full DSP Digital Signal Processor DUT Device Under Test CDCT Clock Drift Compensation Task CQDDR Channel Quality Driven Data Rate EDR Enhanced Data Rate EEPROM Electrically Erasable Programmable Read Only Memory eSCO Extended Synchronous Connection-Oriented (logical transport) EV Extended Voice (packet type) FEC Forward Error Correction FHS Frequency Hop Synchronization (packet) FIFO First In First Out (buffer)
UniStone Acronyms & Abbreviations Acronym or abbreviation Writing out in full LM Link Manager LMP Link Manager Protocol LNA Low Noise Amplifier LO Local Oscillator LPM Low Power Mode(s) LSB Least Significant Bit/Byte LT_ADDR Logical Transport Address MSB Most Significant Bit/Byte MSRS Master-Slave Role Switch NC No Connection NOP No OPeration NVM Non-Volatile Memory OCF Opcode Command Field OGF Opcode Group Field PA Power Amplifier PCB Printed Circuit Board PCM Pulse Coded
UniStone Acronyms & Abbreviations Acronym or abbreviation Writing out in full RTS Request To Send (UART flow control signal) RX Receive RXD Receive Data (UART signal) SCO Synchronous Connection-Oriented (logical transport) SIG Special Interest Group (Bluetooth SIG) SW Software SYRI Synthesizer Reference Input TBD To Be Determined TCK Test Clock (JTAG signal) TDI Test Data In (JTAG signal) TDO Test Data Out (JTAG signal) TL Transport Layer TMS Test Mode Select (JTAG signal) TX Tr
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