Product Info

Bluegiga Technologies Oy
Page 45 of 54
11.3.2 Digital
Digital Terminals Min Typ Max Unit
V
IL
input logic level low 1.7V ≤ VDD ≤ 3.6V
-0.4 - 0.25xVDD V
V
IH
input logic level high 1.7V ≤
VDD ≤ 3.6V
0.7VDD - VDD+0.3 V
V
OL
output logic level low 1.7V ≤ VDD ≤ 3.6V,
(I
o
= 4.0 mA)
--0.125V
V
OH
output logic level high 1.7V ≤ VDD ≤ 3.6V,
(I
o
= -4.0 mA)
VDD-0.4 - VDD V
Stron
g
pull-up
-100 -40 -10
µ
A
Strong pull-down 10 40 100
µ
A
Weak pull-up -5 -1 -0.2
µ
A
Weak pull-down 0.2 1 5
µ
A
I/O pad leakage curren -1 0 1
µ
A
Cl input capacitance 1 - 5 pF
Input Voltage Levels
Output voltage levels
Input Tri-state Current with:
Table 25: Digital terminal electrical characteristics
11.3.3 Reset
Power-on Reset Min Typ Max Unit
VDD_CORE
(a
falling threshold 1.13 1.24 1.3 V
VDD_CORE
(a
rising threshold
1.2 1.31 1.35 V
Hysteresis 0.05 0.07 0.15 V
(a
VDD_CORE is a core voltage supplied by the internal 1.5 V voltage regulator.
Table 26: Power on reset characteristics
11.3.4 32 kHz External Reference Clock
Min Nom Max
Frequency 32748 32768 32788 Hz
Frequency
deviation
@25°C - - 20 +/- ppm
Frequency
deviation
-25°C to 85°C - - 150 +/- ppm
Input high level Square wave 0.625xVDD_PADS - - V
Input low level Square wave - - 0.425xVDD_PADS V
Dut
y
c
y
cle Square wave 30 - 70 %
Rise and fall
time
- - 50 ns
Integrated
frequency jitter
Integrated over
the band 200 Hz
to 15 kHz
---Hz (rms)
UnitsParameter Conditions/Not
es
Specifications
Table 27: External Reference Clock