Product Info

Bluegiga Technologies Oy
TABLE OF CONTENTS
1 Ordering Information ................................................................................................8
2 Pinout and Terminal Description .................................................................................9
3 Microcontroller, Memory and Baseband Logic.............................................................. 12
3.1 AuriStream CODEC............................................................................................ 12
3.1.1 AuriStream CODEC Requirements .................................................................. 13
3.1.2 AuriStream Hierarchy................................................................................... 13
3.2 Memory Managements Unit ................................................................................ 14
3.3 Burst Mode Controller ........................................................................................ 14
3.4 Physical Layer Hardware Engine DSP ................................................................... 14
3.5 WLAN Coexistence ............................................................................................ 15
3.6 Configurable I/O Parallel Ports ............................................................................ 15
4 Clock Generation ....................................................................................................16
4.1 32kHz External Reference Clock .......................................................................... 16
5 Serial Peripheral Interface (SPI) ............................................................................... 17
5.1 WT21 Serial Peripheral Interface (SPI) .................................................................17
5.2 Instruction Cycle............................................................................................... 17
5.2.1 Writing to the Device ................................................................................... 17
5.2.2 Reading from the Device .............................................................................. 18
5.2.3 Multi-Slave Operation................................................................................... 18
6 Host Interfaces ...................................................................................................... 19
6.1 Host Selection .................................................................................................. 19
6.2 UART Interface ................................................................................................. 19
6.2.1 UART Configuration While Reset is Active ........................................................ 21
7 CSR Serial Peripheral Interface (CSPI)....................................................................... 22
7.1.1 CSPI Read/Write Cycles................................................................................ 22
7.1.2 CSPI Register Write Cycle ............................................................................. 23
7.1.3 CSPI Register Read Cycle ............................................................................. 23
7.1.4 CSPI Register Burst Write Cycle..................................................................... 23
7.1.5 CSPI Register Read Cycle ............................................................................. 24
7.2 SDIO Interface .................................................................................................25
7.2.1 SDIO/CSPI Deep-Sleep Control Schemes ........................................................ 25
7.2.2 Retransmission ........................................................................................... 25
7.2.3 Signaling.................................................................................................... 25
8 Audio Interfaces..................................................................................................... 26
8.1 PCM Interface................................................................................................... 26
8.1.1 PCM Interface Master/Slave .......................................................................... 26