User Guide

Creating an FPGA Image DAT File
Appendix D: FPGA Support 199
C:\>datgen tm_fpga_top.stp
DirectC Version 2.x
Copyright (C) 2002 - 2007 Actel Corporation
Checking STAPL file CRC value..
Actual CRC = 7D55
Reading STAPL file...
Generating .dat files...
Image size = 129680
Data compression = 0
Stapl Target ID = 3A121CF
Tool version = 1
Map version = 1
Core Support = 1
FROM support = 0
NVM support = 0
NVM_Block0 support = 0
NVM_Block1 support = 0
NVM_Block2 support = 0
NVM_Block3 support = 0
NVM verifiy = 0
Pass key support = 0
AES key support = 0
Core security Status = 0
From Security Status = 0
NVM_BLOCK0 Security Status = 0
NVM_BLOCK1 Security Status = 0
NVM_BLOCK2 Security Status = 0
NVM_BLOCK3 Security Status = 0
Image CRC = 244B
Done.
C:\>dir *.dat
03/13/2009 02:15 PM 129,680 tm_fpga_top.dat
1 File(s) 129,680 bytes
0 Dir(s) 23,756,279,808 bytes free
3. The resulting tm_fpga_top.dat can now be loaded onto the M6e-TC using the
process described in Loading an FPGA Image
.
WARNING!
When loading an FPGA Image onto the M6e-TC, the Verification process
checks the 16 most significant bits of the FPGA TM and TC version
numbers. To pass, the TM and TC versions must start with 0x1234xxxx
and 0x0010xxxx, respectively. When incrementing version numbers in
the Verilog/VHDL files be sure to only change the 16 least significant
bits.