User Guide

Appendix D: FPGA Support 197
Appendix D: FPGA Support
This appendix explains how to create and update Field Programmable Gate Array
(FPGA) images for the M6e-TC.
Creating an FPGA Image DAT File
Creating an FPGA Image DAT file requires the use of an Actel programming environment.
In the following instructions the use of Libero 8.4 is assumed. The process for other
Libero versions or Actel programming environments may vary. This process assumes
Verilog files have been pre-compiled and you are at the compiling stage.
In order to create an FPGA image DAT file from STAPL output the following programs are
required:
 Libero Designer - Verilog/VHDL complier to build the STAPL (.stp) file.
 datgen.exe - Windows command line tool for converting the STAPL output to a .dat
binary format.
Follow these steps to build the DAT file: