Datasheet

T
T
T
S
S
S
8
8
8
M
M
M
L
L
L
S
S
S
6
6
6
4
4
4
V
V
V
8
8
8
C
C
C
2
2
2
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
Transcend information Inc
8
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter Symbol Value Unit Note
Row active to row active delay tRRD(min) 20 ns 1
/RAS to /CAS delay tRCD(min) 20 ns 1
Row precharge time tRP(min) 20 ns 1
tRAS(min) 50 ns 1
Row active time
tRAS(max) 100 us
Row cycle time tRC(min) 70 ns 1
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3
Number of valid output data CAS latency=2 1 ea 4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.