Datasheet

T
T
T
S
S
S
8
8
8
M
M
M
L
L
L
S
S
S
6
6
6
4
4
4
V
V
V
8
8
8
C
C
C
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL3
Transcend information Inc 10
Serial Presence Detect Specification
Serial Presence Detect
Byte No. Function Described
Standard
Specification
Vendor Part
0 # of Bytes Written into Serial Memory 128bytes
80
1 Total # of Bytes of S.P.D Memory 256bytes
08
2 Fundamental Memory Type SDRAM
04
3 # of Row Addresses on this Assembly 12
0C
4 # of Column Addresses on this Assembly 9
09
5 # of Module Banks on this Assembly 1 bank
01
6 Data Width of this Assembly 64bits
40
7 Data Width Continuation -
00
8 Voltage Interface Standard of this Assembly LVTTL3.3V
01
9 SDRAM Cycle Time (highest CAS latency) 10ns
A0
10 SDRAM Access from Clock (highest CL) 6ns
60
11 DIMM configuration type (non-parity, ECC) Non parity
00
12 Refresh Rate Type
15.625us/Self
Refresh
80
13 Primary SDRAM Width X16
10
14 Error Checking SDRAM Width None
00
15 Min Clock Delay Back to Back Random Address 1 clock
01
16 Burst Lengths Supported 1,2,4,8 & Full page
8F
17 Number of banks on each SDRAM device 4 bank
04
18 CAS # Latency 2 & 3
06
19 CS # Latency 0 clock
01
20 Write Latency 0 clock
01
21 SDRAM Module Attributes Non Buffered
00
22 SDRAM Device Attributes : General
Prec All, Auto Prec,
R/W Burst
0E
23 SDRAM Cycle Time (2
nd
highest CL) 12ns
C0
24 SDRAM Access from Clock (2
nd
highest CL) 7ns
70
25 SDRAM Cycle Time (3
rd
highest CL) -
00
26 SDRAM Access from Clock (3
rd
highest CL) -
00
27 Minimum Row Precharge Time 20ns
14
28 Minimum Row Active to Row Activate 20ns
14
29 Minimum RAS to CAS Delay 20ns
14
30 Minimum RAS Pulse Width 50ns
32
31 Density of Each Bank on Module 1 row of 64MB
10
32 Command/Address Setup Time 2ns
20
33 Command/Address Hold Time 1ns
10
34 Data Signal Setup Time 2ns
20
35 Data Signal Hold Time 1ns
10
36-61 Superset Information -
00