USD410M microSD card Features Description Industrial MLC flash technology Operating Temperature: -25 ~ 85°C Compatible with SD Specification Ver. 5.1 UHS-I with Video Speed Class V10 Application Performance Class1 (A1) NAND flash chips, providing excellent high endurance and performance that help to bring the quality and Early move and Read Retry Built-in ECC and Wear leveling reliability advantages of industrial memory cards RoHS compliant product.
Architecture
Pin Definition SD Mode Pin No.
Specifications Physical Specification Form Factor microSD SD specification SD5.1 (4GB and larger capacity) , SD3.0 (2GB) Dimensions (mm) Length 11.00 ± 0.1 Width 15.00 ± 0.1 Height 0.7 ± 0.1 Operation Condition Min. Typical Max. Vdd Supply Voltage 2.7V 3.3V 3.
Performance Model P/N Sequential Read* Sequential Write* Random Read IOPS** (4KB QD32) TS2GUSD410M 24 8 1800 400 TS4GUSD410M 95 12 3500 700 TS8GUSD410M 95 20 3800 800 TS16GUSD410M 95 30 3500 900 Note: Maximum transfer speed recorded * 25 ℃ , 4GB DRAM, Windows ® 7 with Transcend RDF5, benchmark utility Crystal DiskMark , copied file 1000MB, unit MB/s * *25 ℃ , 4GB DRAM, Windows ® 7 with Transcend RDF5, benchmark IO Meter 2008 , copied 4GB size ,unit IOPS Endurance TS2GUSD410M 5 TS4
Bus Mode/ Power Consumption Value(Max.) Default Mode (25MHz) High Speed mode (50MHz) UHS-I SDR50 mode (100MHz) UHS-I DDR50 mode (50MHz) UHS-I SDR104 mode (208MHz) Read 100mA Write 100mA Idle 0.5mA Read 200mA Write 200mA Idle 0.5mA Read 400mA Write 400mA Idle 0.5mA Read 400mA Write 400mA Idle 0.5mA Read 800mA Write 800mA Idle 0.5mA Note: Power consumption is referred to Section 6.6.3 of the SDA Physical Layer Specification, Version 3.
Product Description 1.Features 1.1 Lock Function Support for password protected locking and unlocking of SD devices. It uses the LOCK/UNLOCK command(CMD42) which is available in SD command sets. 1.2 Built-in ECC Engine In event of errors, the combined data allow the recovery of the original data. The number of errors that can be recovered depends on the algorithm used. 1.3 Wear-leveling This function means the data are no longer tied to a single physical area, which can extend Card’s life expectancy. 1.
2.Bus Topology The SD Memory Card system defines two alternative communication protocols:SD and SPI. The host system can choose either one of modes. The card detects which mode is request by host when the reset command is received and expects all further communication to be in the same communication mode. 2.1 SD Bus For more details, refer to Section 3.5.1 of the SDA Physical Layer Specification, Version 5.1 2.2 SPI Bus For more details, refer to Section 3.5.
3.SD card Register information 3.1 OCR register The OCR 32-bit operation conditions register stores the VDD voltage profile of the non UHS-II card and VDD1 voltage profile of the UHS-II card. Additionally, this register includes status information bits. One status bit is set if the card power up procedure has been finished. This register includes another status bit indicating the card capacity status after set power up status bit 1) This bit is valid only when the card power up status bit is set.
3.2 CID register The Card Identification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase. Every individual flash card shall have a unique identification number. The structure of the CID register is defined in the following paragraphs: • MID An 8-bit binary number that identifies the card manufacturer. The MID number is controlled, defined, and allocated to a SD Memory Card manufacturer by the SD-3C, LLC.
PRV can be customized by Transcend • PSN The Serial Number is 32 bits of binary number. PSN Number can be customized by Transcend • MDT The manufacturing date composed of two hexadecimal digits, one is 8 bit representing the year(y) and the other is four bits representing the month(m). The “m” field [11:8] is the month code. 1 = January. The “y” field [19:12] is the year code. 0 = 2000. As an example, the binary value of the Date field for production date “April 2001” will be: 00000001 0100.
3.3.2 CSD Register Structure (CSD Version 1.
3.3.3 CSD Register (CSD Version 2.0) 3.4 RCA register The writable 16-bit relative card address register carries the card address that is published by the card during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The default value of the RCA 3.
The size of SCR register is 64 bits. This register shall be set in the factory by Transcend. The following table describes the SCR register content The writable 16-bit relative card address register carries the card address that is published by the card during the card identification. This address is used for the addressed host-card communication after the card identification procedure.
4.0 Power Scheme 4.1.1 Power Up Time of Card A card shall be ready to accept the first command within 1ms from detecting VDD min. The host may use up to 74 clocks for preparation before receiving the first command. Power up time is defined as voltage rising time from 0 volt to VDD min and depends on application parameters such as the maximum number of SD Cards, the bus length and the characteristic of the power supply unit.
send the card to SPI mode. CMD8 is newly added in the Physical Layer Specification Version 2.00 to support multiple voltage ranges and used to check whether the card supports supplied voltage. The version 2.00 or later host shall issue CMD8 and verify voltage before card initialization. The host that does not support CMD8 shall supply high voltage range. ACMD41 is a synchronization command used to negotiate the operation voltage range and to poll the cards until they are out of their power-up sequence.
4.1.3 Power On or Power Cycle Followings are requirements for Power on and Power cycle to assure a reliable SD Card hard reset. (1) Voltage level shall be below 0.5V (2) Duration shall be at least 1ms. 4.1.4 Power Supply Ramp Up The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage which is stable between VDD(min.) and VDD(max.) and host can supply SDCLK.
Order information Capacity Transcend Part Number 2GB TS2GUSD410M 4GB TS4GUSD410M 8GB TS8GUSD410M 16GB TS16GUSD410M TAIWAN E-mail: sales-tw@transcend-info.com THE NETHERLANDS E-mail: sales-nl@transcend-info.com USA Los Angeles: E-mail: sales-us@transcend-info.com United Kingdom E-mail: sales-uk@transcend-info.com Maryland: E-mail: sales-us@transcend-info.com Miami: E-mail: sales-us@transcend-info.com Silicon Valley: E-mail: sales-us@transcend-info.com GERMANY E-mail: sales-de@transcend-info.
Revision History Version Date 1.0 2020/04/07 1.1 2020/04/21 1.2 2020/05/15 Note The 1st edition 1. Modify TS2GUSD410M data transfer specification 2. Add TS2GUSD410M & TS16GUSD410M SKU Update TS2GUSD410M Performance & Endurance Copyright © 2020 Transcend Information, Inc.
