Datasheet

R/W/C_P: Writable after value cleared by power failure and H/W reset assertion (the value not
cleared by CMD0 reset) and readable.
R/W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any
CMD0 reset and readable.
W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0
reset and not readable.
Name Field Width Cell
Type
Value CSD-slice
CSD structure CSD_STRUCTURE 2 R 11b [127:126]
System specification
version
SPEC_VERS 4 R 0100b [125:122]
Data read access-time 1 TAAC 8 R 27h [119:112]
Data read access-time 2
in CLK cycles
(NSAC*100)
NSAC 8 R 01h [111:104]
Max. bus clock frequency TRAN_SPEED 8 R 32h [103:96]
Card command classes CCC 12 R 0F5h [95:84]
Max. read data block
length
READ_BL_LEN 4 R 9h [83:80]
Partial blocks for read
allowed
READ_BL_PARTIAL 1 R 0b [79:79]
Write block misalignment WRITE_BLK_MISALIG
N
1 R 0b [78:78]
Read block misalignment READ_BLK_MISALIGN 1 R 0b [77:77]
DSR implemented DSR_IMP 1 R 0b [76:76]
Device size C_SIZE 12 R FFFh [73:62]
Max. read current @ V
DD
min
VDD_R_CURR_MIN 3 R 111b [61:59]
Max. read current @ V
DD
VDD_R_CURR_MAX 3 R 111b [58:56]