Datasheet

ManualsBrandsTranscend Manualscomputer componentsTS64MSS64V6L

144PIN PC133 Unbuffered SO-DIMM

512MB With 32M X 8 CL3

Description

The TS64MSS64V6L is a 64M bit × 64 Synchronous

Dynamic RAM Small Outline Dual In-line Memory Module

(S.O.DIMM), mounted 16 pieces of 256-Mbit SDRAM sealed

in sTSOP package and 1 piece of serial EEPROM (2-kbit)

for Presence Detect (PD). An outline of the products is

144-pin Zig Zag Dual tabs socket type compact and thin

package. Therefore, they make high.

Synchronous design allows precise cycle control with the

use of system clock. I/O transactions are possible on every

clock cycle. Range of operation frequencies, programmable

latencies allow the same device to be useful for a variety of

high bandwidth, high performance memory system

applications.

Features

• Performance Range: PC-133

• Conformed to JEDEC Standard 2 clocks.

• Burst Mode Operation.

• Auto and Self Refresh.

• CKE Power Down Mode.

• DQM Byte Masking (Read/Write)

• Serial Presence Detect (SPD) with serial EEPROM

• LVTTL compatible inputs and outputs.

• Single 3.3V ± 0.3V power supply.

• MRS cycle with address key programs.

Latency (Access from column address)

Burst Length (1,2,4,8)

Data Sequence (Sequential & Interleave)

• All inputs are sampled at the positive going edge of

the system clock.

•

DRAM brand: Promos.

•

Operating Temperature TA: 0~70 °C

Symbol Function

A0~A12, BA0,BA1

Address input

DQ0~DQ63, Data Input / Output.

CLK0, CLK1

Clock Input.

CKE0, CKE1

Clock Enable Input.

/CS0~/CS3

Chip Select Input.

/RAS

Row Address Strobe

/CAS

Column Address Strobe

/WE

Write Enable

DQM0~DQM7

Data (DQ) Mask

SA0~SA2

Address in EEPROM

SCL

Serial PD Clock

SDA

Serial PD Add/Data input/output

Vcc

+3.3 Voltage Power Supply

Vss

Ground

No Connection

Pin Identification

Transcend information Inc.

Summary of content (10 pages)

PAGE 1
44PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L Description The TS64MSS64V6L is a 64M bit × 64 Synchronous Dynamic RAM Small Outline Dual In-line Memory Module Symbol (S.O.DIMM), mounted 16 pieces of 256-Mbit SDRAM sealed Function A0~A12, BA0,BA1 Address input in sTSOP package and 1 piece of serial EEPROM (2-kbit) DQ0~DQ63, Data Input / Output. CLK0, CLK1 Clock Input. CKE0, CKE1 Clock Enable Input. /CS0~/CS3 Chip Select Input.
PAGE 2
144PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L Dimension: B D A F C E G H K I J PCB: 09-2260 Side Millimeters Inches A 67.60 ± 0.20 2.661 ± 0.008 B 32.80 1.291 C 23.20 0.913 D 4.60 0.181 E 3.30 0.130 F 2.50 0.098 G 4.00 0.157 H 6.00 0.236 I 20.00 0.787 J 29.21± 0.20 1.150± 0.008 K 1.00 ± 0.10 0.040 ± 0.004 Transcend information Inc.
PAGE 3
144PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L Pinouts: Pin Pin Pin Pin No Name No Name 01 Vss 49 DQ13 03 DQ0 51 DQ14 05 DQ1 53 DQ15 07 DQ2 55 Vss 09 DQ3 57 *CB0 11 Vcc 59 *CB1 13 DQ4 61 CLK0 15 DQ5 63 Vcc 17 DQ6 65 /RAS 19 DQ7 67 /WE 21 Vss 69 /CS0 23 DQM0 71 */CS1 25 DQM1 73 NC 27 Vcc 75 Vss 29 A0 77 *CB2 31 A1 79 *CB3 33 A2 81 Vcc 35 Vss 83 DQ16 37 DQ8 85 DQ17 39 DQ9 87 DQ18 41 DQ10 89 DQ19 43 DQ11 91 Vss 45 Vcc 93 DQ20 47 DQ12 95 DQ21 * Please refer Block Diagram Pin No 97 99 101
PAGE 4
144PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L Block Diagram /CS CLK CKE A0~A12,BA0,1 DQ0~DQ7 A0~A12,BA0,1 DQ0~DQ7 A0~A12,BA0,1 DQ0~DQ7 /RAS /CAS 32Mx8 /WE SDRAM /RAS /CAS 32Mx8 /WE SDRAM /CS CLK CKE /RAS /CAS 32Mx8 /WE SDRAM /CS CLK CKE DQM7 DQM DQM DQM6 A0~A12,BA0,1 DQ0~DQ7 /RAS /CAS 32Mx8 /WE SDRAM /CS CLK CKE /CS CLK CKE /CS CLK CKE /CS CLK DQM0 DQM1 CKE DQM A0~A12,BA0,1 DQ0~DQ7 /RAS /CAS 32Mx8 /WE SDRAM DQM A0~A12,BA0,1 DQ0~DQ7 /RAS /CAS 32Mx8 /WE SDRAM DQM A
PAGE 5
144PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply to Vss Storage temperature Power dissipation Short circuit current Operating Temperature Note: Symbol VIN, VOUT VDD, VDDQ TSTG PD Ios TA Value -1.0 to +4.6 -1.0 to +4.6 -55 to +125 12.7 50 0 ~ 70 Unit V V °C W mA °C Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
PAGE 6
144PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L Parameter Operating Current (One Bank Active) Symbol ICC1 Precharge Standby Current ICC2P in power-down mode ICC2PS ICC2N Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) ICC2NS Test Condition CAS Latency Burst Length =1 tRC≥tRC(min) IOL=0mA CKE≤VIL(max), tCC=12ns CKE & CLK≤VIL(max), tCC=∞ Input signals are changed one time during
PAGE 7
144PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 65°C) Parameter Value Unit 2.4/0.4 V 1.4 V tr/tf=1/1 ns 1.4 V AC Input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 Vtt=1.4V 3.3V 50 Ohm 1200 Ohm Output Output VOH (DC)=2.4V, I OH=-2mA VOL (DC)=0.4V, I OL=2mA Z0=50 Ohm 50pF 50pF 870 Ohm (Fig.
PAGE 8
144PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Refresh Auto Refresh Self Entry Refresh Exit Bank Active & Row Addr.
PAGE 9
144PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L Serial Presence Detect Specification Serial Presence Detect Byte No. Function Described Standard Specification Vendor Part 0 Number of Bytes Written into Serial Memory 128bytes 80 1 Total Number of Bytes of S.P.
PAGE 10
144PIN PC133 Unbuffered SO-DIMM 512MB With 32M X 8 CL3 TS64MSS64V6L 31 Density of Each Bank on Module 1row of 256MB 40 32 Command/Address Setup Time 1.5ns 15 33 Command/Address Hold Time 0.8ns 08 34 Data Signal Setup Time 1.5ns 15 35 Data Signal Hold Time 0.8ns 08 00 12 53 7F,4F 54 36-61 62 63 64-71 72 Superset Information SPD Data Revision Code Checksum for Bytes 0-62 Manufacturers JEDEC ID Dode per JEP-108E Manufacturing Location Intel Ver1.