Datasheet

ManualsBrandsTranscend Manualscomputer componentsTS64MSD64V6J

200PIN DDR266 Unbuffered SO-DIMM

512MB With 64Mx8 CL2.5

Description

The TS64MSD64V6J is a 64M x 64bits Double Data Rate

SDRAM high-density for DDR266.The TS64MSD64V6J

consists of 8pcs CMOS 64Mx8 bits Double Data Rate

SDRAMs in 66 pin TSOP-II 400mil packages, and a 2048

bits serial EEPROM on a 200-pin printed circuit board.

The TS64MSD64V6J is a Dual In-Line Memory Module

and is intended for mounting into 200-pin edge connector

sockets.

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible

on both edges of DQS. Range of operation frequencies,

programmable latencies allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

Features

• Power supply : VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V

• Max clock Freq : 133MHZ.

• Double-data-rate architecture; two data transfers per

clock cycle

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transition with CK transition

• Auto and Self Refresh 7.8us refresh interval.

• Data I/O transactions on both edge of data strobe.

• Edge aligned data output, center aligned data input.

• Serial Presence Detect (SPD) with serial EEPROM

• SSTL-2 compatible inputs and outputs.

• MRS cycle with address key programs.

CAS Latency (Access from column address) : 2.5

Burst Length (2,4,8 )

Data Sequence (Sequential & Interleave)

Placement

PCB:09-1220

Transcend Information Inc.

Summary of content (12 pages)

PAGE 1
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J Description Placement The TS64MSD64V6J is a 64M x 64bits Double Data Rate SDRAM high-density for DDR266.The TS64MSD64V6J consists of 8pcs CMOS 64Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP-II 400mil packages, and a 2048 bits serial EEPROM on a 200-pin printed circuit board. B The TS64MSD64V6J is a Dual In-Line Memory Module A and is intended for mounting into 200-pin edge connector F sockets.
PAGE 2
00PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J Dimensions Side Pin Identification Millimeters Inches Symbol Function A 67.60±0.20 2.661±0.008 A0~A12,BA0,BA1 Address input B 47.40 1.866 DQ0~DQ63 Data Input / Output. C 11.40 0.449 DQS0~DQS7 Data strobe input/output D 4.20 0.165 E 2.15 0.085 CK0~CK1 Clock Input. F 1.80 0.071 G 6.00 0.236 H 18.00 0.709 I 20.00 J K /CK0~CK1 CKE0 Clock Enable Input. /CS0 Chip Select Input. 0.
PAGE 3
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.
PAGE 4
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.
PAGE 5
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply to Vss VDD, VDDQ -1.0 ~ 3.
PAGE 6
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J DC CHARACTERISTICS (Recommended operating condition unless otherwise noted,VDD=2.7V TA = 10°C) Parameter Operating current - One bank Active-Precharge; tRC=tRCmin; tCK= tCK min DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle Operating current - One bank Active-Read-Precharge; Burst=2; tRC=tRC min; CL=2.
PAGE 7
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J AC OPERATING CONDITIONS Parameter Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) Input Differential Voltage, CK and /CK inputs VID(AC) Input Crossing Point Voltage, CK and /CK inputs VIX(AC) Note: Max Unit V 3 VREF - 0.31 V 3 0.7 VDDQ + 0.6 V 1 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 V 2 Note 1.
PAGE 8
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J AC Timing Parameters & Specifications (These AC characteristics were tested on the Component) Parameter Symbol Min Max Unit Row cycle time tRC 65 ns Refresh row cycle time tRFC 75 ns Row active time tRAS 45 /RAS to /CAS delay tRCD 20 ns Row active to Row active delay tRP 20 ns Row active to Row active delay tRRD 15 ns Write recovery time tWR 15 tCK Last data in to Read command tCDLR 1 tCK Col.
PAGE 9
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J DQ & DM hold time to DQS tDH 0.5 ns DQ & DM input pulse width tDIPW 1.75 ns Power down exit time tPDEX 7.5 Ns Exit self refresh to bank active command tXSA 75 ns Exit self refresh to read command tXSR 200 Cycle Refresh interval time tREF 7.8 us Clock half period tHP tCLmin or ns 5 1 tCHmin Data hold skew factor tQHS DQS write postamble time tWPST Note: 0.4 0.75 Ns 0.6 TCK 3 1.
PAGE 10
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J SIMPLIFIED TRUTH TABLE COMMAND Extended Mode Register Set Mode Register Set Auto Refresh Entry Self Refresh Exit Register Register Refresh Bank Active & Row Addr.
PAGE 11
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J Serial Presence Detect Specification Serial Presence Detect Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function Described # of Bytes Written into Serial Memory Total # of Bytes of S.P.
PAGE 12
200PIN DDR266 Unbuffered SO-DIMM 512MB With 64Mx8 CL2.5 TS64MSD64V6J 72 Manufacturing Location T 54 54 53 36 34 4D 53 73-90 Manufacturers Part Number TS64MSD64V6J 44 36 34 56 36 4A 20 20 20 20 20 20 91-92 93-94 95-98 99-127 128~255 Revision Code Manufacturing Date Assembly Serial Number Manufacturer Specific Data Unused Storage Locations Transcend Information Inc.