Datasheet

T
T
T
S
S
S
6
6
6
4
4
4
M
M
M
M
M
M
D
D
D
6
6
6
4
4
4
V
V
V
6
6
6
F
F
F
512MB 172 PIN PC266 DDR
MICRO-DIMM With 32Mx8 2.5VOLT
Transcend Information Inc.
9
DQ & DM hold time to DQS tDH 0.5 ns
DQ & DM input pulse width tDIPW 1.75 ns
Power down exit time tPDEX 7.5 ns
Exit self refresh to bank active command tXSA 75 ns 5
Exit self refresh to read command tXSR 200 Cycle
Refresh interval time tREF 7.8 us 1
Clock half period tHP tCLmin or
tCHmin
ns
Data hold skew factor tQHS 0.75 ns
DQS write postamble time tWPST 0.4 0.6 TCK 3
Note: 1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown
(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a
previous write was in progress, DQS could be High at this time, depending on tDQSS.
3. The Maximum limit for this parameter is not a device limit. The device will operate with a great value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
4. For registered DIMMs, tCL and tCH are >= 45% of the period including both the half period jitter (tJIT(HP) ) of
the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
5. A write command can be applied with tRCD satisfied after this command.