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240PIN DDR2 800 Unbuffered DIMM

512MB With 64Mx8 CL5

Transcend Information Inc.

Description Placement

The TS64MLQ64V8J is a 64M x 64bits DDR2-800

Unbuffered DIMM. The TS64MLQ64V8J consists of 8 pcs

64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages

and a 2048 bits serial EEPROM on a 240-pin printed

circuit board. The TS64MLQ64V8J is a Dual In-Line

Memory Module and is intended for mounting into 240-pin

edge connector sockets.

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible

on both edges of DQS. Range of operation frequencies,

programmable latencies allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

Features

• RoHS compliant product.

• JEDEC standard 1.8V ± 0.1V Power supply.

• VDDQ=1.8V ± 0.1V

• Max clock Freq: 400MHZ; 800Mb/S/Pin.

• Posted CAS

• Programmable CAS Latency: 3,4,5

• Programmable Additive Latency :0, 1,2,3 and 4

• Write Latency (WL) = Read Latency (RL)-1

• Burst Length: 4,8(Interleave/nibble sequential)

PCB: 09-2280

• Programmable sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended

data-strobe is an optional feature)

• Off-Chip Driver (OCD) Impedance Adjustment

• MRS cycle with address key programs.

• On Die Termination

• Serial presence detect with EEPROM

Summary of content (11 pages)

PAGE 1
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Description Placement The TS64MLQ64V8J is a 64M x 64bits DDR2-800 Unbuffered DIMM. The TS64MLQ64V8J consists of 8 pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 240-pin printed circuit board. The TS64MLQ64V8J is a Dual In-Line B Memory Module and is intended for mounting into 240-pin edge connector sockets. D E Synchronous design allows precise cycle control with the F use of system clock.
PAGE 2
40PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Dimensions Pin Identification Side Millimeters Inches Symbol Function A 133.35±0.15 5.250±0.006 A0~A13, BA0, BA1 Address input B 55 2.165 DQ0~DQ63 Data Input / Output. C 63 2.480000 DQS0~DQS7 Data strobe D 5 0.197 /DQS0~/DQS7 Differential Data strobe E 2.5 0.0980 F 1.5±0.10 0.059±0.039 G 5.175 0.204 H 2.2 0.867 I 4 0.157 CKE0, CKE1 Clock Enable Input. J 10 0.
PAGE 3
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Pinouts: Pin Pin Pin Pin Pin Pin No Name No Name No Name 01 VREF 41 VSS 81 DQ33 02 VSS 42 *CB0 82 VSS 03 DQ0 43 *CB1 83 /DQS4 04 DQ1 44 VSS 84 DQS4 05 VSS 45 */DQS8 85 VSS 06 /DQS0 46 *DQS8 86 DQ34 07 DQS0 47 VSS 87 DQ35 08 VSS 48 *CB2 88 VSS 09 DQ2 49 *CB3 89 DQ40 10 DQ3 50 VSS 90 DQ41 11 VSS 51 VDDQ 91 VSS 12 DQ8 52 CKE0 92 /DQS5 13 DQ9 53 VDD 93 DQS5 14 VSS 54 NC 94 VSS 15 /DQS1 55 NC 95 DQ42 16 DQS1 56 VDDQ 96 DQ43 17 VSS 57 A11 97 VSS 1
PAGE 4
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Block Diagram /CS0 /DQS0 DQS0 DM0 /DQS4 DQS4 DM4 DM /CS DQS /DQS DM /CS DQS /DQS DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 U1 /DQS1 DQS1 DM1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 U5 /DQS5 DQS5 DM5 DM /CS DQS /DQS DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM /CS DQS /DQS DQ 40
PAGE 5
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Absolute Maximum DC Ratings Parameter Symbol Value Unit Notes Voltage on VDD relative to Vss VDD -1.0 ~ 2.3 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.5 ~ 2.3 V 1 Voltage on VDDL pin relative to Vss VDDL -0.5 ~ 2.3 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 2.3 V 1 Storage temperature TSTG -55~+100 °C 1,2 Note: 1.
PAGE 6
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J IDD Specification parameters Definition ( IDD values are for full operating range of voltage and Temperature) Parameter Symbol Max.
PAGE 7
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Input AC Logic Level Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Symbol VIH(AC) VIL(AC) Min VREF + 0.200 Max Unit VREF - 0.200 V V Note AC Input Test Condition Condition Symbol Value Unit Note Input reference voltage VREF 0.5*VDDQ V 1 Input signal maximum peak to peak swing VSWING(MAX) 1.0 V 1 Input signal minimum slew rate SLEW 1.0 V/ns 2,3 Note: 1.
PAGE 8
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Timing Parameters & Specifications (These AC characteristics were tested on the Component) Parameter Symbol tAC Min -400 Max +400 Unit ps tDQSCK -350 +350 ps CK high-level width tCH 0.45 0.55 tCK CK low-level width tCL 0.45 0.
PAGE 9
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J Four Activate Window for 2KB page size products tFAW 45 ns /CAS to /CAS command delay tCCD 2 tCK Write recovery time tWR 15 X ns Auto precharge write recovery + precharge time tDAL tWR+tRP X tCK Internal write to read command delay tWTR 7.5 X ns Internal read to precharge command delay tRTP 7.
PAGE 10
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J SERIAL PRESENCE DETECT SPECIFICATION Serial Presence Detect Byte No. 0 1 2 3 4 Function Described # of Serial PD Bytes written during module production Total # of Bytes of S.P.
PAGE 11
240PIN DDR2 800 Unbuffered DIMM 512MB With 64Mx8 CL5 TS64MLQ64V8J 37 38 39 40 41 42 43 44 45 46 47~61 62 63 64-71 72 Internal write to read command delay(=tWTR) Internal read to precharge command delay(=tRTP) Memory analysis probe characteristics Extension of Byte41 tRC and Byte42 tRFC DDR SDRAM Minimum Active to Active/Auto Refresh Time(tRC) DDR SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) DDR SDRAM Maximum Device Cycle Time (tCK max) DDR SDRAM DQS-DQ Skew for DQS and associate