Datasheet
T
T
T
S
S
S
6
6
6
4
4
4
M
M
M
L
L
L
D
D
D
7
7
7
2
2
2
V
V
V
6
6
6
F
F
F
5
5
5
184PIN DDR266 Unbuffered DIMM
512MB With 32Mx8 CL2.5
Description
The TS64MLD72V6F5 is a 64M x 72bits Double
Data Rate SDRAM high-density for DDR266. The
TS64MLD72V6F5 consists of 18pcs CMOS 32Mx8 bits
Double Data Rate SDRAMs in 66 pin TSOP-II 400mil
packages and a 2048 bits serial EEPROM on a 184-pin
printed circuit board. The TS64MLD72V6F5 is a Dual
In-Line Memory Module and is intended for mounting into
184-pin edge connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• Power supply: VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V
• Max clock Freq: 133MHZ.
• Double-data-rate architecture; two data transfers per
clock cycle
• Differential clock inputs(CK and /CK)
• DLL aligns DQ and DQS transition with CK transition
• Auto and Self Refresh 7.8us refresh interval.
• Data I/O transactions on both edge of data strobe.
• Edge aligned data output, center aligned data input.
• Serial Presence Detect (SPD) with serial EEPROM.
• SSTL-2 compatible inputs and outputs.
• MRS cycle with address key programs.
CAS Latency (Access from column address) : 2.5
Burst Length (2,4,8 )
Data Sequence (Sequential & Interleave)
Placement
I
A
B
D
C
H
G
F
E
PCB : 09- 0920
Transcend Information Inc.
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