Datasheet

T
T
T
S
S
S
6
6
6
4
4
4
M
M
M
L
L
L
D
D
D
7
7
7
2
2
2
V
V
V
4
4
4
F
F
F
3
3
3
184PIN DDR400 ECC Unbuffered DIMM
512MB With 32Mx8 CL3
Transcend Information Inc.
7
AC OPERATING CONDITIONS
Parameter Symbol Min Max
Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V 3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V 3
Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V 1
Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 V 2
Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the
DC level of the same.
3. These parameters should be tested at the pin on actual components and may be checked at either the pin
or the pad in simulation. The AC and DC input specifications are relative to a VREF envelope that has been
bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS (VDD=2.6, VDDQ=2.6, TA=0 to 70°C)
Parameter Value Unit Note
Input reference voltage for Clock 0.5*VDDQ V
Input signal maximum peak swing 1.5 V
Input Levels (VIH/VIL) VREF+0.31/VREF-0.31 V
Input timing measurement reference level VREF V
Output timing measurement reference level VTT V
Output load condition See Load Circuit
ZO=50ohm
VTT=0.5*VDDQ
RT=50ohm
C
LOAD =30pF
Output
Output Load circuit
VREF
=0.5*VDDQ
Input/Output CAPACITANCE
(VDD = 2.6V, VDDQ = 2.6V,TA = 25°C, f = 1MHz)
Parameter Symbol Min Max Unit
Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)
Input capacitance (CKE0,CKE1)
Input capacitance (/CS0,/CS1)
Input capacitance (CK0~CK2)
Input capacitance (DM0~DM8)
Data and DQS input/output capacitance (DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
C
IN1
CIN2
C
IN3
C
IN4
CIN5
C
OUT1
COUT2
69
44
44
28
10
10
10
87
53
53
34
12
12
12
pF
pF
pF
pF
pF
pF
pF