Datasheet

T
T
T
S
S
S
6
6
6
4
4
4
M
M
M
L
L
L
D
D
D
7
7
7
2
2
2
V
V
V
4
4
4
F
F
F
3
3
3
184PIN DDR400 ECC Unbuffered DIMM
512MB With 32Mx8 CL3
Transcend Information Inc.
6
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, VDD=2.7V TA = 10°C)
Parameter Symbol Max. Unit Note
Operating current - One bank Active-Precharge; tRC=tRCmin;
DQ, DM and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle
IDD0 1,620 mA
Operating current - One bank operation; One bank open, Burst=4; Reads
- Refer to the following page for detailed test condition.
IDD1 1,850 mA
Percharge power-down standby current; All banks idle; power –down mode;
CKE = <VIL(max); VIN = VREF for DQ,DQS and DM
IDD2P 75 mA
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); Address and other control inputs changing once per clock
cycle; VIN = VREF for DQ,DQS and DM
IDD2F 540 mA
Active power - down standby current ; one bank active; power-down mode;
CKE<= VIL (max); VIN = VREF for DQ,DQS and DM
IDD3P 990 mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax;
DQ, DQS and DM inputs changing twice per clock cycle;
address and other control inputs changing once per clock cycle
IDD3N 1,350 mA
Operating current - burst read; Burst length = 2; reads; continuous burst;
One bank active; address and control inputs changing once per clock cycle;
50% of data changing at every burst; lout = 0 mA
IDD4R 2,340 mA
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
DQ, DM and DQS inputs changing twice per clock cycle,
50% of input data changing at every burst
IDD4W 2,660 mA
Auto refresh current; tRC = tRFC(min),
10*tCK for DDR400 at 200Mhz; distributed refresh
IDD5 2,480 mA
Self refresh current; CKE <= 0.2V; External clock should be on;
IDD6 54 mA
Operating current - Four bank operation; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7 3830 mA
Note: 1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading capacitor.