Datasheet

T
T
T
S
S
S
6
6
6
4
4
4
M
F
M
M
L
L
L
D
D
D
6
6
6
4
4
4
V
V
V
6
6
6
F
F
5
5
5
184PIN DDR266 Unbuffered DIMM
512MB With 32Mx8 CL2.5
Transcend Information Inc.
7
AC OPERATING CONDITIONS
Parameter Symbol
VREF+0.31/VREF-0.31 V
Min Max
Unit
Input timing measurement reference level VREF V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC)
Output timing measurement reference level
VREF + 0.31 V
VTT V
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Output load condition See Load Circuit
VIL(AC) VREF - 0.31 V
3
Input Differential Voltage, CK and /CK inputs
Input/Output CAPACITANCE
(VDD = 2.5V, VDDQ = 2.5V,TA = 25°C, f = 1MHz)
Parameter Symbol
VID(AC) 0.7 VDDQ + 0.6
Min Max Unit
V 1
Input Crossing Point Voltage, CK and /CK inputs
Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)
Input capacitance (CKE0, CKE1)
Input capacitance (/CS0, /CS1)
VIX(AC) 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2
Input capacitance (CK0~CK2)
Input capacitance (DM0~DM7)
Data and DQS input/output capacitance (DQ0~DQ63)
V 2
C
IN1
CIN2
C
IN3
Note:
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
C
IN4
CIN5
C
OUT1
65
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the
DC level of the same.
42
42
27
3. These parameters should be tested at the pin on actual components and may be checked at either the pin or
the pad in simulation. The AC and DC input specifications are relative to a VREF envelope that has been
bandwidth limited 20MHz.
10
10
81
AC OPERATING TEST CONDITIONS
(VDD=2.5, VDDQ=2.5, TA=0 to 70°C)
Parameter Value Unit
50
50
34
13
Note
Input reference voltage for Clock
13
pF
pF
0.5*VDDQ V
pF
pF
pF
Input signal maximum peak swing 1.5 V
pF
Input Levels(VIH/VIL)
ZO=50ohm
VTT=0.5*VDDQ
RT=50ohm
C
LOAD
=30pF
Output
Output Load circuit
VREF
=0.5*VDDQ