Datasheet

T
T
T
S
S
S
6
6
6
4
4
4
M
M
M
D
D
D
R
R
R
7
7
7
2
2
2
V
V
V
4
4
4
F
F
F
3
3
3
184 PIN DDR400 Registered DIMM
512MB With 32Mx8 CL3
Transcend Information Inc.
7
AC OPERATING CONDITIONS
Parameter
Input Levels(VIH/VIL) VREF+0.31/VREF-0.31 V
pF
Symbol Min Max
Input timing measurement reference level
Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VREF V
VIH(AC) VREF + 0.31
Output timing measurement reference level VTT V
V 3
Output load condition
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31
See Load Circuit
V 3
Input/Output CAPACITANCE (VDD = 2.5V, VDDQ = 2.5V,TA = 25°C, f = 1MHz)
Input Differential Voltage, CK and /CK inputs VID(AC) 0.7
Parameter Symbol Min
VDDQ + 0.6 V 1
Max Unit
Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)
Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ - 0.2
Input capacitance (CKE0, CKE1)
Input capacitance (/CS0, /CS1)
Input capacitance (CLK0, /CLK0)
0.5*VDDQ + 0.2 V 2
Input capacitance (DM0~DM8)
Data and DQS input/output capacitance (DQ0~DQ63)
Data input/output capacitance(CB0~CB7)
Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
CIN1
CIN2
CIN3
CIN4
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the
DC level of the same.
CIN5
COUT1
COUT2
3. These parameters should be tested at the pin on actual components and may be checked at either the pin
or the pad in simulation the AC and DC input specifications are relative to a VREF envelope that has been
bandwidth limited 20MHz.
9
9
9
AC OPERATING TEST CONDITIONS (VDD=2.5, VDDQ=2.5, TA=0 to 70°C)
Parameter Value
11
14
14
14
Unit Note
11
Input reference voltage for Clock 0.5*VDDQ V
12
16
16
Input signal maximum peak swing 1.5
16
pF
pF
pF
V
pF
pF
pF
ZO=50ohm
VTT=0.5*VDDQ
RT=50ohm
C
LOAD =30pF
Output
Output Load circuit
VREF
=0.5*VDDQ
11
11