TS32G~ TS32G~256 256GPSD330 256GPSD330 2.5” Solid State Disk Description Features Transcend PSD is a series of 2.5 PATA SSD RoHS compliant products with high performance and advanced flash control Supports LBA 48bit addressing. techniques. Due to smaller size (fit the standard Fully compatible with devices and OS that support the IDE standard (44-Pin, pitch = 2.
TS32G~ TS32G~256 256GPSD330 256GPSD330 2.5” Solid State Disk Specifications Physical Specification Form Factor 2.5-inch HDD Storage Capacities 32 GB to 256 GB Dimensions (mm) Length 100.3 0 0.40 Width 69.85 0.20 Height 7.40 0.15 Input Voltage 5V 10% Weight 55g 5g Connector 44-Pin standard IDE/ATA connector (Pitch 2.
TS32G~ TS32G~256 256GPSD330 256GPSD330 2.5” Solid State Disk Performance(Sandisk 15nm) Sequential Read Sequential Write Random 4K Read Random 4K Write 32GB 120 45 12.28 1.455 64GB 120 45.87 12.85 1.606 128GB 120 75.19 14.64 1.794 Note : Test by Crystal Disk Mark V3.0.1, 500MB size @25 oC, P5K-VM(ICH 9), 1GB RAM * 2, IDE interface support up to UDMA6, Windows® XP SP3 Power consumption (mA) Capacity 32GB 64GB 128GB 256GB Read 240.9 236.8 240.1 223 Write 158.9 245.5 247.
TS32G~ TS32G~256 256GPSD330 256GPSD330 2.5” Solid State Disk Environmental Specifications Operating Temperature 0oC to 70 oC Storage Temperature -40 oC to 85 oC Operating Humidity (Non condensation) 0% to 95% Storage Humidity (Non condensation) 0% to 95% SHOCK & Vibration Test Condition Standard Mechanical Shock Test 1500G, 0.
TS32G~ TS32G~256 256GPSD330 256GPSD330 2.5” Solid State Disk *Note: Tighten mounting screws with no more than 2.0Kg-cm (0.14ft-lbs) of torque. Transcend Information Inc. 5 V1.
TS32G~ TS32G~256 256GPSD330 256GPSD330 2.5” Solid State Disk Pin Assignments Pin No. Pin Name Pin No.
TS32G~ TS32G~256 256GPSD330 256GPSD330 2.5” Solid State Disk Block Diagram Transcend Information Inc. 7 V1.
Reliability 1. Global Wear Leveling – Advanced algorithm to enhance the Wear-Leveling Efficiency There are 3 main processes in SMI global wear leveling approaches: A. Record the block erase count and save in the wear-leveling table. B. Find the static-block and save it in wear-leveling pointer. C. Check the erase count when the block popped from spare pool. If the block erase count is bigger than WEARCNT, then it swapped the static-block and over-count-block.
prevents the host from sending in further address/instructions/data that may be corrupted. During power disturbance, the host is likely experiencing a voltage drop, so the transmission integrity cannot be guaranteed. Second, it stops the information sending to the Flash. This prevents the controller from corrupting the address/data being transmitted to the Flash, and corrupting the Flash contents inadvertently.
Support ATA/ATAPI Command List Support ATA/ATAPI Command Code Protocol EXECUTE DIAGNOSTICS 90h Device diagnostic FLUSH CACHE E7h Non-data IDENTIFY DEVICE ECh PIO data-In READ DMA C8h DMA READ MULTIPLE C4h PIO data-In General Feature Set READ SECTOR(S) 20h PIO data-In 40h or 41h Non-data SET FEATURES EFh Non-data SET MULTIPLE MODE C6h Non-data WRITE DMA CAh DMA WRITE MULTIPLE C5h PIO data-out WRITE SECTOR(S) 30h PIO data-out NOP 00h Non-data READ BUFFER E4h PIO dat
General Feature Set FLUSH CACHE (E7h) This command is used by the host to request the device to flush the write cache. If there is data in the write cache, that data shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs. IDENTIFY DEVICE (ECh) This commands read out 512 Bytes of drive parameter information. Parameter Information consists of the arrangement and value as shown in the following table.
Word Address 62 63 64 65 66 67 68 69 -79 80 81 82 83 84 Default value Total Bytes (Hex) 0x0000 2 0x0007 2 0x0003 2 0x0078 2 0x0078 2 0x0078 2 0x0078 2 0x0000 22 0x0800 2 0x0000 2 0x7028 2 0x5000 2 0x4000 2 Data Field Type Information Reserved Multiword DMA transfer Advanced PIO modes supported Minimum Multiword DMA transfer cycle time per word Recommended Multiword DMA transfer cycle time.
READ DMA (C8h) Read data from sectors during Ultra DMA and Multiword DMA transfer. Use the SET FEATURES command to specify the mode value. A sector count of zero requests 256 sectors. READ MULTIPLE (C4h) This command performs similarly to the Read Sectors command. Interrupts are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command.
WRITE BUFFER (E8h) This command enables the host to write the contents of one 512-byte block of data to the device’s buffer. Power Management Feature Set CHECK POWER MODE (E5h or 98h) The host can use this command to determine the current power management mode. IDLE (E3h or 97h) This command causes the device to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled.
Security Mode Feature Set SECURITY SET PASSWORD (F1h) This command set user password or master password. The host outputs sector data with PIO data-out protocol to indicate the information defined in the following table.
SECURITY ERASE UNIT (F4h) The host uses this command to transfer 512 bytes of data, as shown in the following table, to the drive. The transferred data contains a user or master password, which the drive compares with the saved password. If they match, the drive deletes user data, disables the user password, and cancels the lock. The master password is still saved. It is re-enabled by issuing the SECURITY SET PASSWORD command to re-set a user password.
SMART Feature Set Transcend IDE SSD supports the SMART command set and define some vendor-specific data to report spare/bad block numbers in each memory management unit. Individual SMART commands are identified by the value placed in the Feature register. Table shows these Feature register values.
SMART RETURN STATUS B0h with a Feature register value of DAh. This command causes the device to communicate the reliability status of the device to the host. If a threshold exceeded condition is not detected by the device, the device shall set the LBA Mid register to 4Fh and the LBA High register to C2h. If a threshold exceeded condition is detected by the device, the device shall set the LBA Mid register to F4h and the LBA High register to 2Ch.
SMART DATA Structure The following 512 bytes make up the device SMART data structure. Users can obtain the data by SMART command.
SMART Attributes The following table defines the vendor specific data in byte 2 to 361 of the 512-byte SMART data.
Ultra DMA data transfer Ultra DMA data burst timing requirements Name Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Measurement (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) location Min t2CYCTYP tCYC t2CYC tDS tDH tDVS tDVH tCS tCH tCVS tCVH tZFS tDZFS tMLI tUI tZAD tENV tACK tSS Max Min Max Min Max Min Max Min Max 90 60 40 30 Sender 112 73 54 39 25 16.8 13.0 Note 3 230 153 115 86 57 38 29 Sender 15.0 10.0 7.0 7.0 5.0 4.0 2.
Name Comment t2CYCTYP Typical sustained average two cycle time tCYC Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) t2CYC Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) tDS Data setup time at recipient (from data valid until STROBE edge) tDH Data hold time at recipient (from STROBE edge until data may become invalid) tDVS Data valid setup time at sender (from data va
Initiating an Ultra DMA data-in burst
Sustained Ultra DMA data-in burst Host pausing an Ultra DMA data-in burst
Device terminating an Ultra DMA data-in burst
Host terminating an Ultra DMA data-in burst
Initiating an Ultra DMA data-out burst
Sustained Ultra DMA data-out burst Device pausing an Ultra DMA data-out burst
Host terminating an Ultra DMA data-out burst
Device terminating an Ultra DMA data-out burst
Multiword DMA data transfer For Multiword DMA modes 1 and above, the minimum value of t0 is specified by word 65 in the IDENTIFY DEVICE parameter list. Table 50 defines the minimum value that shall be placed in word 65. Devices shall power-up with mode 0 as the default Multiword DMA mode.
Initiating a Multiword DMA data burst
Sustaining a Multiword DMA data burst
Device terminating a Multiword DMA data burst
Host terminating a Multiword DMA data burst
PIO data transfer PIO timing requirements PIO timing parameters Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 ns ns ns ns ns t0 Cycle time (min) 600 383 240 180 120 t1 Address valid to DIOR-/DIOW- setup (min) 70 50 30 30 25 t2 DIOR-/DIOW- (min) 165 125 100 80 70 t2i DIOR-/DIOW- recovery time (min) - - - 70 25 t3 DIOW- data setup (min) 60 45 30 30 20 t4 DIOW- data hold (min) 30 20 15 10 10 t5 DIOR- data setup (min) 50 35 20 20 20 t6 DIOR- data hold (m
PIO data transfer to/from device
Ordering Information Capacity 32G Model P/N TS32GPSD330 64G TS64GPSD330 128G TS128GPSD330 256G TS256GPSD330 The above technical information is based on industry standard data and has been tested to be reliable. However, Transcend makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes to the specifications at any time without prior notice. TAIWAN No.70, XingZhong Rd.
