Datasheet

384-551
End User Programmable
-
-
TS2GHR72V1Z Serial Presence Detect
Byte No.
Function Described
Standard Specification
Vendor Part
0
Number of Bytes Used / Number of Bytes in SPD
Device / CRC Coverage
CRC:0-255Byte
SPD Byte use: 512Byte
SPD Byte total: 512Byte
24
1
SPD Revision
-
-
2
Key Byte / DRAM Device Type
DDR4 SDRAM
0C
3
Key Byte / Module Type
RDIMM
01
4
SDRAM Density and Banks
4Gb, 16banks
84
5
SDRAM Addressing
ROW:16, Column:10
21
6
SDRAM Package Type
-
-
7
SDRAM Optional Features
-
-
8
SDRAM Thermal and Refresh Options
-
-
9
Other SDRAM Optional Features
-
-
10
Reserved
-
00
11
Module Nominal Voltage, VDD
1.2V
03
12
Module Organization
2Rank, 4bits
08
13
Module Memory Bus Width
ECC, 72bits
0B
14
Module Thermal Sensor
Support
80
15-16
Reserved
-
00
17
Timebases
-
00
18
SDRAM Minimum Cycle Time (tCKAVGmin)
0.938ns
08
19
SDRAM Maximum Cycle Time (tCKAVGmax)
1.5ns
0C
20-23
CAS Latencies Supported
10, 11, 12, 13, 14, 15, 16
-
24
Minimum CAS Latency Time (tAAmin)
13.75ns
6E
25
Minimum RAS to CAS Delay Time (tRCDmin)
13.75ns
6E
26
Minimum Row Precharge Delay Time (tRPmin)
13.75ns
6E
27
Upper Nibbles for tRASmin and tRCmin
-
11
28
Minimum Active to Precharge Delay Time (tRASmin),
Least Significant Byte
33ns
08
29
Minimum Active to Active/Refresh Delay Time
(tRCmin), Least Significant Byte
46.75ns
76
30-31
Minimum Refresh Recovery Delay Time (tRFC1min)
260ns
20,08
32-33
Minimum Refresh Recovery Delay Time (tRFC2min)
160ns
00,05
34-35
Minimum Refresh Recovery Delay Time (tRFC4min)
110ns
70,03
36-37
Minimum Four Activate Window Delay Time
(tFAWmin)
15ns
00,78
38
Minimum Activate to Activate Delay Time
(tRRD_Smin), different bank group
3.7ns
1E
39
Minimum Activate to Activate Delay Time
(tRRD_Lmin), same bank group
5.3ns
2B
40
Minimum CAS to CAS Delay Time (tCCD_Lmin),
same bank group
5.625ns
2E
41-59
Reserved
-
00