Datasheet

same bank group
41-59
Reserved
-
00
60-77
Connector to SDRAM Bit Mapping
-
-
78-116
Reserved
-
00
117
Fine Offset for Minimum CAS to CAS Delay Time
(tCCD_Lmin), same bank group
-
83
118
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Lmin), same bank group
-
B5
119
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Smin), different bank group
-
CE
120
Fine Offset for Minimum Active to Active/Refresh
Delay Time (tRCmin)
-
00
121
Fine Offset for Minimum Row Precharge Delay Time
(tRPmin)
-
00
122
Fine Offset for Minimum RAS to CAS Delay Time
(tRCDmin)
-
00
123
Fine Offset for Minimum CAS Latency Time (tAAmin)
-
00
124
Fine Offset for SDRAM Maximum Cycle Time
(tCKAVGmax)
-
00
125
Fine Offset for SDRAM Minimum Cycle Time
(tCKAVGmin)
-
C2
126-127
Cyclical Redundancy Code
-
-
128
Raw Card Extension, Module Nominal Height
31.25mm
11
129
Module Maximum Thickness
Planar Double Sides
11
130
Reference Raw Card Used
Revision 0, Raw card C
02
131
DIMM Module Attributes
1 Row,1 Register
05
132
RDIMM Thermal Heat Spreader Solution
Not incorporated
00
133-134
Register Manufacturer ID Code
By Manufacturer
Variable
135
Register Revision Number
By Manufacturer
Variable
136
Address Mapping from Register to DRAM
Not Mirrored
00
137
Register Output Drive Strength for Control
Moderate Drive:
Chip select, ODT, CKE
Moderate Drive:
Command/Address
55
138
Register Output Drive Strength for CK
Moderate Drive
05
139-253
Reserved
-
00
254-255
Cyclical Redundancy Code (CRC)
-
-
256-319
Reserved
-
00
320-321
Module Manufacturer ID Code
-
-
322
Module Manufacturing Location
-
-
323-324
Module Manufacturing Date
-
-
325-328
Module Serial Number
-
-
329-348
Module Part Number
-
-
349
Module Revision Code
-
00
350-351
DRAM Manufacturer ID Code
By Manufacturer
Variable
352
DRAM Stepping
-
00
353-381
Manufacturer Specific Data
By Manufacturer
Variable
382-383
Reserved
-
00