Description Features The Transcend CF 300 is a High Speed Compact • CompactFlash Specification Version 4.1 Complaint Flash Card with high quality Flash Memory assembled • RoHS compliant products on a printed circuit board. • Single Power Supply: 3.
Ordering Information Part Number Interface Transfer Mode Disk Type Ultra DMA mode 0~5 (UDMA5 as default) True IDE mode Multi-Word DMA Mode 0~4 TS128M~16GCF300 Fixed Disk (Default) PIO Mode 0 ~ 6 PC Card mode (PCMCIA) Ultra DMA mode 0~5 Removable (Default) C.H.
Performance Model P/N Read (MB/s) Write (MB/s) Random Read (MB/s) Random Write (MB/s) TS128MCF300 21 5 10 0.1 TS256MCF300 40 9 13 0.1 TS512MCF300 21 8 10 0.1 TS1GCF300 21 8 9 0.1 TS2GCF300 30 12 10 0.1 TS4GCF300 59 24 11 0.2 TS8GCF300 57 35 11 1.5 TS16GCF300 56 37 11 1.5 * Note : 25 ℃, according to CF to IDE connector test on P5K-VM, 1GB RAM * 2, IDE interface support UDMA5, Windows® XP Version 2002 SP3, benchmark utility CrystalDisk (version 3.
SHOCK & Vibration Test Condition Mechanical Shock Test Vibration Test 1500G, 0.
More Functions to extend product life 1. Global Wear Leveling – Advanced algorithm to enhance the Wear-Leveling Efficiency There are 3 main processes in global wear leveling approaches: (1) Record the block erase count and save in the wear-leveling table. (2) Find the static-block and save it in wear-leveling pointer. (3) Check the erase count when the block popped from spare pool. If the block erase count is bigger than WEARCNT, then swapped the static-block and over-count-block.
Transcend
Block Diagram
Pin Assignments and Pin Type
Note: 1) These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow for 3-state signals not to consume current. 2) The signal should be grounded by the host. 3) The signal should be tied to VCC by the host. 4) The mode is required for CompactFlash Storage Cards. 5) The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled upon the card in these modes, it should not be left floating by the host in PC Card modes.
Signal Description Signal Name Dir. A10 – A00 (PC Card Memory Mode) I Pin 8,10,11,12, These address lines along with the -REG signal are used to select the following: 14,15,16,17, The I/O port address registers within the CompactFlash Storage Card , the 18,19,20 memory mapped port address registers within the CompactFlash Storage Card, a byte in the card's information structure and its configuration control and status registers.
the odd byte of the word.-CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2. A multiplexing scheme based on A0,-CE1, -CE2 allows 8 bit hosts to access all data on D0-D7. See Table 27, Table 29, Table 31, Table 35, Table 36 and Table 37. (PC Card Memory Mode) Card Enable This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode) Input Acknowledge when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the CompactFlash Storage Card and the CPU. DMARQ (True IDE Mode) This signal is a DMA Request that is used for DMA data transfers between host and device. It shall be asserted by the device when it is ready to transfer data to or from the host.
The clocking shall occur on the negative to positive edge of the signal (trailing edge). -IOWR (True IDE Mode – Except Ultra DMA Protocol Active) In True IDE Mode, while Ultra DMA mode protocol is not active, this signal has the same function as in PC Card I/O Mode. When Ultra DMA mode protocol is supported, this signal must be negated before entering Ultra DMA mode protocol.
While DMA operations are not active, the card shall ignore the -DMACK signal, including a floating condition. If DMA operation is not supported by a True IDE Mode only host, this signal should be driven high or connected to VCC by the host. A host that does not support DMA mode and implements both PCMCIA and True-IDE modes of operation need not alter the PCMCIA mode connections while in True-IDE mode as long as this does not prevent proper operation all modes.
-WAIT (PC Card Memory Mode) O 42 -WAIT (PC Card I/O Mode) The -WAIT signal is driven low by the CompactFlash Storage Card to signal the host to delay completion of a memory or I/O cycle that is in progress. This signal is the same as the PC Card Memory Mode signal. In True IDE Mode, except in Ultra DMA modes, this output signal may be used as IORDY.
2. Input Power 3. Input Leakage Current 4. Input Characteristics CompactFlash interface I/O at 5.0V Parameter Symbol Min. Max. 5.5 Supply Voltage VCC 4.5 High level output voltage VOH VCC-0.8 Low level output voltage VOL High level input voltage VIH Low level input voltage VIL Pull up resistance 2 Pull down resistance Unit Remark V V 0.8 V 4.0 V Non-schmitt trigger 2.92 V Schmitt trigger1 0.8 V Non-schmitt trigger 1.70 V Schmitt trigger1 RPU 50.
Symbol Min. Max. Unit Supply Voltage Parameter VCC 2.7 3.6 V High level output voltage VOH 2.4 Low level output voltage VOL 0.4 V High level input voltage VIH V Non-schmitt trigger 1.4 2.0 V Schmitt trigger Low level input voltage VIL 0.8 V Non-schmitt trigger 0.8 1.2 V Schmitt trigger Pull up resistance RPU 40 kOhm Pull down resistance RPD 40 kOhm V 2.0 1. Include CE1, CE2, HREG, HOE. HIOE, HWE, HIOW pins. 2. Include CE1, CE2, HREG, HOE.
11.
Signal Interface
Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF 10 at a DC current of 700 μA low state and 150 μA high state, including pull-resistor. The socket shall be able to drive at least the following load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF with DC current 700 μA low state and 150 μA high state per socket). 2) Resistor is optional.
Ultra DMA Electrical Requirements Host and Card signal capacitance limits for Ultra DMA operation The host interface signal capacitance at the host connector shall be a maximum of 25 pF for each signal as measured at 1 MHz. The card interface signal capacitance at the card connector shall be a maximum of 20 pF for each signal as measured at 1 MHz.
Table: Ultra DMA Termination with Pull-up or Pull down Example Printed Circuit Board (PCB) Trace Requirements for Ultra DMA On any PCB for a host or device supporting Ultra DMA: The longest D[15:00] trace shall be no more than 0.5" longer than either STROBE trace as measured from the IC pin to the connector. The shortest D[15:00] trace shall be no more than 0.5" shorter than either STROBE trace as measured from the IC pin to the connector.
Attribute Memory Read Timing Specification
Configuration Register (Attribute Memory) Write Timing Specification
Common Memory Read Timing Specification
Common Memory Write Timing Specification
I/O Input (Read) Timing Specification 4.
5.
True IDE Ultra DMA Mode Read/Write Timing Specification Table: Ultra DMA Data Burst Timing Requirements
Notes: 1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V. 2) All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column. For example, in the case of tRFS, both STROBE and –DMARDY transitions are measured at the sender connector. 3) The parameter tCYC shall be measured at the recipient’s connector farthest from the sender.
Notes: 1) The parameters tUI, tMLI : (Ultra DMA Data-In Burst Device Termination Timing and Ultra DMA Data-In Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender
interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum. 2) 80-conductor cabling shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times in modes greater than 2.
Table: Ultra DMA Sender and Recipient IC Timing Requirements Note: 1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point. All other signals should remain connected through to the recipient.
Card Configuration The CompactFlash Storage Cards is identified by appropriate information in the Card Information Structure (CIS). The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system.
Attribute Memory Function Attribute memory is a space where CompactFlash Storage Card identification and configuration information are stored, and is limited to 8 bit wide accesses only at even addresses. The card configuration registers are also located here. For CompactFlash Storage Cards, the base address of the ard configuration registers is 200h.
Configuration Option Register (Base + 00h in Attribute Memory)
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I/O Transfer Function The I/O transfer to or from the CompactFlash Storage can be either 8 or 16 bits. When a 16 bit accessible port is addressed, the signal -IOIS16 is asserted by the CompactFlash Storage. Otherwise, the -IOIS16 signal is de-asserted. When a 16 bit transfer is attempted, and the -IOIS16 signal is not asserted by the CompactFlash Storage, the system shall generate a pair of 8 bit references to access the word‘s even byte and odd byte.
Common Memory Transfer Function The Common Memory transfer to or from the CompactFlash Storage can be either 8 or 16 bits.
True IDE Mode I/O Transfer Function The CompactFlash Storage Card can be configured in a True IDE Mode of operation. The CompactFlash Storage Card is configured in this mode only when the -OE input signal is grounded by the host during the power off to power on cycle. Optionally, CompactFlash Storage Cards may support the following optional detection methods: 1. The card is permitted to monitor the –OE (-ATA SEL) signal at any time(s) and switch to PCMCIA mode upon detecting a high level on the pin. 2.
Metaformat Overview The goal of the Metaformat is to describe the requirements and capabilities of the CompactFlash Storage Card as thoroughly as possible. This includes describing the power requirements, IO requirements, memory requirements, manufacturer information and details about the services provided. Table: Sample Device Info Tuple Information for Extended Speeds Note: The value “1” defined for D3 of the N+0 words indicates that no write-protect switch controls writing the ATA registers.
CF-ATA Drive Register Set Definition and Protocol The CompactFlash Storage Card can be configured as a high performance I/O device through: a) The standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary) or 170h- 177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ). b) Any system decoded 16 byte I/O block using any available IRQ. c) Memory space.
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Memory Mapped Addressing When the CompactFlash Storage Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2K bytes as follows: True IDE Mode Addressing When the CompactFlash Storage Card is configured in the True IDE Mode, the I/O decoding is as follows:
CF-ATA Registers The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the “task file.” Data Register (Address - 1F0h[170h];Offset 0,8,9) The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register.
Feature Register (Address - 1F1h[171h]; Offset 1, 0Dh Write Only) This register provides information regarding features of the CompactFlash Storage Card that the host can utilize. This register is also accessed in PC Card modes on data bits D15-D8 during a write operation to Offset 0 with -CE2 low and -CE1 high.
Bit 2 (HS2): when operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode. Bit 1 (HS1): when operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode. Bit 0 (HS0): when operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode.
Device Control Register (Address - 3F6h[376h]; Offset Eh) This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows: Bit 7: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0. Bit 6: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.
Card (Drive) Address Register (Address 3F7h[377h]; Offset Fh) This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not be mapped into the host’s I/O space because of potential conflicts on Bit 7. Bit 7: this bit is unknown. Implementation Note: Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the CompactFlash Storage Card.
CF-ATA Command Set
Request Sense - 03h The extended error code is returned to the host in the Error Register.
1) Erase Sector(s) - C0h This command is used to pre-erase and condition data sectors in advance of a Write without Erase or Write Multiple without Erase command. There is no data transfer associated with this command but a Write Fault error status can occur.
Translate Sector Information
Set Features – EFh Feature Supported Feature 03h 81h 82h Operation Set transfer mode based on calue in Sector Count register Disable 8 bit data transfer Disable Write Cache 2) Execute Drive Diagnostic - 90h When the diagnostic command is issued in a PCMCIA configuration mode, this command runs only on the CompactFlash Storage Card that is addressed by the Drive/Head register.
3) Flush Cache – E7h This command causes the card to complete writing data from its cache. The card returns status with RDY=1 and DSC=1 after the data in the write cache buffer is written to the media. If the Compact Flash Storage Card does not support the Flush Cache command, the Compact Flash Storage Card shall return command aborted. 4) Identify Device – ECh The Identify Device command enables the host to receive parameter information from the CompactFlash Storage Card.
Read Multiple - C4h Read Sector(s) - 20h or 21h Read Verify Sector(s) - 40h or 41h Set Multiple Mode - C6h
Write DMA – CAh Write Multiple Command - C5h Write Sector(s) - 30h or 31h
NOP - 00h This command always fails with the CompactFlash Storage Card returning command aborted. Read Buffer - E4h The Read Buffer command enables the host to read the current contents of the CompactFlash Storage Card’s sector buffer. This command has the same protocol as the Read Sector(s) command.
Check Power Mode - 98h or E5h If the CompactFlash Storage Card is in, going to, or recovering from the sleep mode, the CompactFlash Storage Card sets BSY, sets the Sector Count Register to 00h, clears BSY and generates an interrupt. If the CompactFlash Storage Card is in Idle mode, the CompactFlash Storage Card sets BSY, sets the Sector Count Register to FFh, clears BSY and generates an interrupt.
Set Sleep Mode- 99h or E6h Standby - 96h or E2h Standby Immediate - 94h or E0h
Security Set Password – F1h Table Security Unlock – F2h
Security Erase Prepare – F3h Security Erase Unit – F4h Security Freeze Lock – F5h
Security Freeze Lock – F6h 6) Format Track - 50h This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically FFh or 00h). To remain host backward compatible, the CompactFlash Storage Card expects a sector buffer of data from the host to follow the command with the same protocol as the Write Sector(s) command although the information in the buffer is not used by the CompactFlash Storage Card.
Recalibrate - 1Xh Seek - 7Xh Wear Level - F5h Write Verify - 3Ch
Error Posting
Error and Status Register summarizes the valid status and error value for all the CF-ATA Command set.
ID Table Information of True IDE Mode Word Address Default Value Total Bytes 044Ah 2 General configuration - signature for the CompactFlash Flash Storage Card 0XXX 2 General configuration – Bit Significant with ATA-4 definitions.
67 0078h 2 Minimum PIO transfer cycle time without flow control 68 0078h 2 Minimum PIO transfer cycle time with IORDY flow control 69-79 0000h 20 Reserved 80-81 0000h 4 Reserved – CF cards do not return an ATA version 82 702Bh 2 Command sets supported 83 500Ch 2 Command sets supported 84 4000h 2 Command sets supported 85-87 XXXXh 6 Features/command sets enabled 88 003Fh 2 Ultra DMA Mode Supported and Selected 89 0001h 2 Time required for Security erase unit completi
If bits 15:12 are set to 8h then Word 0 shall be 848Ah. If bits 15:12 are set to 0h then Bits 11:0 are set using the definitions below and the Card is required to support for the CFA command set and report that in bit 2 of Word 83. Bit 15:12 values other than 8h and 0h are prohibited. Bits 11-8: Retired These bits have retired ATA bit definitions.
If bit 13 is set to 1 then the Standby timer is supported as defined by the IDLE command If bit 13 is set to 0 then the Standby timer operation is defined by the vendor. Bit 11: IORDY Supported If bit 11 is set to 1 then this CompactFlash Storage Card supports IORDY operation. If bit 11 is set to 0 then this CompactFlash Storage Card may support IORDY operation. Bit 10: IORDY may be disabled Bit 10 shall be set to 0, indicating that IORDY may not be disabled.
Card supports Multiword DMA modes 2, 1 and 0. Support for Multiword DMA modes 3 and above are specific to CompactFlash are reported in word 163, Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings. Word 64: Advanced PIO transfer modes supported Bits 7 through 0 of word 64 of the Identify Device parameter information is defined as the advanced PIO data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant.
15 of word 83 and word 84 shall be cleared to zero to provide indication that the features/command sets supported words are valid. The values in these words should not be depended on by host implementers. Bit 0 of word 82 shall be set to zero; the SMART feature set is not supported. If bit 1 of word 82 is set to one, the Security Mode feature set is supported. Bit 2 of word 82 shall be set to zero; the Removable Media feature set is not supported.
Bit 0 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Download Microcode command. Bit 1 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Read DMA Queued and Write DMA Queued commands. If bit 2 of word 86 shall be set to one, the CompactFlash Storage Card supports the CFA feature set. If bit 3 of word 86 is set to one, the Advanced Power Management feature set has been enabled via the Set Features command.
If set to 1, indicates that the Enhanced security erase unit feature set is supported. Bit 4: Expire If set to 1, indicates that the security count has expired and Security Unlock and Security Erase Unit are command aborted until a power-on reset or hard reset. Bit 3: Freeze If set to 1, indicates that the security is Frozen. Bit 2: Lock If set to 1, indicates that the security is locked. Bit 1: Enable/Disable If set to 1, indicates that the security is enabled.
Value 0 1 2 3-7 DMA mode supported by the card. Maximum Multiword DMA timing mode supported Specified in word 63 Multiword DMA Mode 3 Multiword DMA Mode 4 Reserved Value 0 1 2 3-7 Bits 8-6: Advanced True IDE PIO Mode Selected Indicates the current True IDE PIO mode selected on the card.
SMART Command Set 1) SMART Command Set SMART Feature Register Values D0h Read Data D5h Read Log D1h Read Attribute Threshold D6h Write Log D2h Enable/Disable Autosave D8h Enable SMART Operations D3h Save Attribute Values D9h Disable SMART Operations D4h Execute OFF-LINE Immediate DAh Return Status If reserved size is below the Threshold, the status can be read from Cylinder register by Return Status command (DAh).
406 F Number of max pair 407-410 X Vendor specific 411-510 X Vendor specific 511 V Data structure checksum F=the content of the byte is fixed and does not change. V=the content of the byte is variable and may change depending on the state of the device or the commands executed by the device. X=the content of the byte is vendor specific and may be fixed or variable. R=the content of the byte is reserved and shall be zero.
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Version Date 2.2 2014/2/26 2.4 2014/6/19 3.0 2014/7/09 3.1 2015/12/21 Revision History Modification Content Add 128M~1GCF300 module update 128M~1GCF300 module, add power shield information, add revision history update 4G~8GCF300 module performance 1. Modify document format 2. Modify SMART Data Structure 3. Advanced Power Shield description 4. Add Host termination suggestion 5.
