Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
S
S
S
D
D
D
6
6
6
4
4
4
V
V
V
4
4
4
F
F
F
3
3
3
200PIN DDR400 Unbuffered SO-DIMM
256MB With 32Mx8 CL3
Transcend Information Inc.
8
AC Timing Parameters & Specifications
(These AC characteristics were tested on the Component)
Parameter Symbol Min Max Unit Note
Row cycle time tRC 60 ns
Refresh row cycle time tRFC 70 ns
Row active time tRAS 40 70K ns
/RAS to /CAS delay tRCD 18 ns
Row active to Row active delay tRP 18 ns
Row active to Row active delay tRRD 10 ns
Write recovery time tWR 15 ns
Internal write to read command delay tWTR 2 tCK
Clock cycle time tCK 5 10 ns 16
Clock high level width tCH 0.45 0.55 tCK
Clock low level width tCL 0.45 0.55 tCK
DQS-out access time from CK /CK tDQSCK -0.55 0.55 ns
Output data access time from CK /CK tAC -0.65 0.65 ns
Data strobe edge to output data edge tDQSQ 0.4 ns 13
Read Preamble tRPRE 0.9 1.1 tCK
Read Postamble tRPST 0.4 0.6 tCK
CK to valid DQS-in tDQSS 0.72 1.28 tCK
Write preamble setup time tWPRES 0 ps 5
Write preamble tWPRE 0.25 tCK
Write postamble tWPST 0.4 0.6 tCK 4
DQS falling edge to CK rising-setup time tDSS 0.2 tCK
DQS falling edge from CK rising-hold time tDSH 0.2 tCK
DQS-in high level width tDQSH 0.35 tCK
DQS-in low level width tDQSL 0.35 tCK
Address and Control input setup time tIS 0.6 ns 7~10
Address and Control input hold time tIH 0.6 ns 7~10
Data-out high-impedance time from CK, /CK tHZ - 0.65 ns 3
Data-out low-impedance time from CK, /CK tLZ -0.65 0.65 ns 3
Mode register set cycle time tMRD 2 tCK
DQ & DM setup time to DQS tDS 0.4 ns
DQ & DM hold time to DQS tDH 0.4 ns
DQ & DM input pulse width tDIPW 1.75 ns 9
Control &Address input pulse width for each input tIPW 2.2 ns 9
Refresh interval time tREF 7.8 us 6
Output DQS valid window TQH tHP-0.55 ns 12
Clock half period tHP tCLmin/tCHmin ns 11,12