Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
S
S
S
D
D
D
6
6
6
4
4
4
V
V
V
3
3
3
F
F
F
5
5
5
200PIN DDR333 Unbuffered SO-DIMM
256MB With 32Mx8 CL2.5
Transcend Information Inc.
9
Data-out low-impedance time from CK, /CK tLZ -0.7 0.7 ns
Mode register set cycle time tMRD 12 ns
Control & Address input pulse width
(for each input)
tIPW 2.2 ns
DQ & DM input pulse width tDIPW 1.75 ns
Exit self refresh to non read command tXSNR 75 ns 5
Exit self refresh to read command tXSRD 200 tCK
Refresh interval time tREF 7.8 us 1
Output DQS valid window tQH tHP-tQHS ns 4
Clock half period tHP tCLmin or
tCHmin
ns
Data hold skew factor tQHS 0.55 ns
DQS write postamble time tRAP tRCD or
tRAS min
ns 3
Auto Precharge Write recovery +
Precharge time
tDAL (tWR/tCK) +
(tRP/tCK)
tCK 5
Note: 1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown
(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a
previous write was in progress, DQS could be High at this time, depending on tDQSS.
3. The Maximum limit for this parameter is not a device limit. The device will operate with a great value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
4. For registered DIMMs, tCL and tCH are >= 45% of the period including both the half period jitter (tJIT(HP) ) of
the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
5. A write command can be applied with tRCD satisfied after this command.