Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
S
S
S
D
D
D
6
6
6
4
4
4
V
V
V
3
3
3
F
F
F
5
5
5
200PIN DDR333 Unbuffered SO-DIMM
256MB With 32Mx8 CL2.5
Transcend Information Inc.
8
AC Timing Parameters & Specifications
(These AC characteristics were tested on the Component)
Parameter Symbol Min Max Unit Note
Row cycle time tRC 60 ns
Refresh row cycle time tRFC 72 ns
Row active time tRAS 42 70K ns
/RAS to /CAS delay tRCD 18 ns
Row active to Row active delay tRP 18 ns
Row active to Row active delay tRRD 12 ns
Write recovery time tWR 15 ns
Last data in to Read command tCDLR 1 tCK
Col. Address to Col. Address delay tCCD 1 tCK
Clock cycle time tCK 6 12 ns 4
Clock high level width tCH 0.45 0.55 tCK
Clock low level width tCL 0.45 0.55 tCK
DQS-out access time from CK /CK tDQSCK -0.6 0.6 ns
Output data access time from CK /CK tAC -0.7 0.7 ns
Data strobe edge to output data edge tDQSQ 0.45 ns 4
Read Preamble tRPRE 0.9 1.1 tCK
Read Postamble tRPST 0.4 0.6 tCK
CK to valid DQS-in tDQSS 0.75 1.25 tCK
DQS-in setup time tWPRES 0 ns 2
Write Preamble tWPRE 0.25 tCK
Write Postamble tWPST 0.4 0.6 tCK
DQS falling edge to CK rising-setup time tDSS 0.2 tCK
DQS falling edge from CK rising-hold time tDSH 0.2 tCK
DQS-in high level width tDQSH 0.35 tCK
DQS-in low level width tDQSL 0.35 tCK
Address and Control input setup/hold time (fast
slew rate)
tIS/tIH 0.75 ns
Address and Control input setup/hold time (slow
slew rate)
tIS/tIH 0.8 ns
DQ & DM setup time to DQS tDS 0.45 ns
DQ & DM hold time to DQS tDH 0.45 ns
Data-out high-impedance time from CK, /CK tHZ -0.7 0.7 ns