Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
M
M
M
S
S
S
6
6
6
4
4
4
V
V
V
6
6
6
F
F
F
144PIN PC133 MICRO SO-DIMM
256MB With 32M X 8 CL3
Transcend information Inc. 7
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Row cycle time
Parameter Value Unit
tRC(min) 65 ns 1
AC Input levels (VIH/VIL) 2.4/0.4 V
Last data in to new col. Address delay tCDL(min)
Input timing measurement reference level 1.4
1 CLK 2
V
Input rise and fall time tr/tf=1/1
Last data in to row precharge tRDL(min) 2
ns
Output timing measurement reference level
CLK 2
1.4 V
Last data in to Active delay tDAL 2CLK+tRP
Output load condition See Fig. 2
-
Last data in to burst stop
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
tBDL(min) 1 CLK
Output
(Fig. 1) DC Output Load Circuit
3.3V
1200 Ohm
50pF
870 Ohm
V
OH (DC)=2.4V, I OH =-2mA
V
OL (DC)=0.4V, I OL =2mA
Output
(Fig. 2) AC Output Load Circuit
Vtt=1.4V
50 Ohm
50pF
Z0=50 Ohm
Symbol
Value
Unit
2
Col. address to col. address delay
Note
tCCD(min) 1 CLK 3
Row active to row active delay tRRD(min) 15 ns 1
Number of valid output data
CAS latency=2
/RAS to /CAS delay tRCD(min)
1
ea 4
20 ns 1
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
Row precharge time tRP(min) 20
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
ns 1
tRAS(min) 45
Row active time
ns 1
tRAS(max) 100 us