Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
L
L
L
S
S
S
7
7
7
2
2
2
V
V
V
6
6
6
D
D
D
168PIN PC133 Unbuffered DIMM
256MB With 16Mx8 CL3
Parameter Value
Row cycle time
t
RC(min)
65
Unit
AC Input levels (VIH/VIL)
ns 1
2.4/0.4 V
Last data in to row precharge tRDL(min) 2
Input timing measurement reference level 1.4 V
CLK 2
Last data in to Active precharge
Input rise and fall time tr/tf=1/1 ns
tDAL(min) 2 CLK + 20ns -
Output timing measurement reference level 1.4
Last data in to new col. address delay
V
Output load condition See Fig. 2
tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min)
Output
(Fig. 1) DC Output Load Circuit
3.3V
1200 Ohm
50pF
870 Ohm
V
OH (DC)=2.4V, I OH =-2mA
V
OL (DC)=0.4V, I OL =2mA
Output
(Fig. 2) AC Output Load Circuit
Vtt=1.4V
50 Ohm
50pF
Z0=50 Ohm
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter Symbol
1 CLK 2
Value Unit Note
Col. address to col. address delay tCCD(min) 1
Row active to row active delay tRRD(min) 15
CLK 3
ns 1
CAS latency=3 2
Number of valid output data
/RAS to /CAS delay tRCD(min) 20 ns
ea 4
1
Row precharge time tRP(min) 20 ns
Note:
1
tRAS(min)
Row active time
1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
45 ns 1
2. Minimum delay is required to complete write.
t
RAS(max)
3. All parts allow every cycle column address change.
100 us
4. In case of row precharge interrupt, auto precharge and read burst stop.
CAS latency=2 -
Transcend Information Inc.
7