Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
5
M
M
L
L
L
Q
Q
Q
7
7
7
2
2
2
V
V
V
5
5
F
F
F
240PIN DDR2 533 Unbuffered DIMM
256MB With 32Mx8 CL4
Transcend Information Inc.
7
Input AC Logic Level
Parameter Symbol
Symbol Min Max
Min Max Unit
Unit
Input capacitance (CK0 and /CK0)
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input capacitance (CK1 and /CK1)
Input capacitance (CK2 and /CK2)
Input capacitance (CKE0 and /CS)
Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)
VIH(AC) VREF + 0.250 V
Input capacitance (DQ, DM, DQS, /DQS)
CCK0
CCK1
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
CCK2
CI
1
CI2
VIL(AC) VREF - 0.250
CIO
-
-
V
-
-
-
-
AC Input Test Condition
Condition Symbol
25
25
25
Value Unit Note
44
44
6
Input reference voltage VREF 0.5*VDDQ
pF
pF
pF
pF
V 1
pF
pF
Input signal maximum peak to peak swing
Note:
DM is internally loaded to match DQ and DQS identically.
VSWING(MAX) 1.0 V 1
Input signal minimum slew rate SLEW
1.0 V/ns 2,3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the
device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising
edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions
and VIH(AC) to VIL(AC) on the negative transitions.
V SWING(MAX)
delta TF
delta TR
VDD
V
IH (AC) min
V IH (DC) min
VREF
V
IL (DC) max
V IL (AC) max
VSS
Falling Slew=
VREF-VIL(AC)max
delta TF
Rising Slew=
VIH(AC)min-VREF
delta TR
AC Input Test Signal Waveform
Input/Output Capacitance
(VDD = 1.8V, VDDQ = 1.8V, TA = 25°C)
Parameter