Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
L
L
L
D
D
D
7
7
7
2
2
2
V
V
V
6
6
6
F
F
F
5
5
5
256MB 184 PIN DDR266 DDR SDRAM
DIMM With 32Mx8 2.5VOLT
Transcend Information Inc.
6
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, VDD=2.7V TA = 10°C)
Parameter Symbol Max. Unit Note
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK= tCK min
DQ, DM and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle
IDD0 1035 mA
Operating current - One bank Active-Read-Precharge; Burst=2;
tRC=tRC min; CL=2.5; tCK=tCK min; VIN=VREF fro DQ,DQS and DM
IDD1 1350 mA
Percharge power-down standby current; All banks idle;
power –down mode; CKE = <VIL(max); tCK= tCK min
VIN = VREF
for DQ, DQS and DM
IDD2P 252 mA
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=133Mhz for DDR266
Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ, DQS and DM
IDD2F 450 mA
Active power - down standby current ; one bank active; power-down mode; CKE<=
VIL (max); tCK = tCK min;
VIN = VREF for DQ, DQS and DM
IDD3P 405 mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = tCK min;
DQ, DQS and DM inputs changing twice per clock cycle; address and other control
inputs changing once per clock cycle
IDD3N 585 mA
Operating current - burst read; Burst length = 2; reads; continuous burst; One
bank active; address and control inputs changing once per clock cycle; CL=2.5 at
tCK = tCK min; 50% of data changing at every burst; lout = 0 mA
IDD4R 1980 mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One
bank active address and control inputs changing once per clock cycle; CL=2.5 at
tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle, 50% of
input data changing at every burst
IDD4W 2655 mA
Auto refresh current; tRC = tRFC(min)
IDD5 1980 mA
Self refresh current; CKE <= 0.2V;
IDD6 27 mA
Operating current - Four bank operation;
Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7 3555 mA
Note: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading cap.