Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
L
L
L
D
D
D
7
7
7
2
2
2
V
V
V
3
3
3
F
F
F
184PIN DDR333 ECC Unbuffered DIMM
256MB with 32Mx8 CL2.5
Transcend Information Inc.
10
Serial Presence Detect Specification
Serial Presence Detect
Byte No. Function Described Standard
Specification
Vendor Part
0 # of Bytes Written into Serial Memory 128bytes 80
1 Total # of Bytes of S.P.D Memory 256bytes 08
2 Fundamental Memory Type DDR SDRAM 07
3 # of Row Addresses on this Assembly 13 0D
4 # of Column Addresses on this Assembly 10 0A
5 # of Module Rows on this Assembly 1 bank 01
6 Data Width of this Assembly 72bits 48
7 Data Width of this Assembly 0 00
8 VDDQ and Interface Standard of this Assembly SSTL 2.5V 04
9 DDR SDRAM Cycle Time at CAS Latency=2.5 6ns 60
10 DDR SDRAM Access Time from Clock at CL=2.5
±0.7ns
70
11 DIMM configuration type (non-parity, Parity, ECC) ECC 02
12 Refresh Rate Type 7.8us/Self Refresh 82
13 Primary DDR SDRAM Width X8 08
14 Error Checking DDR SDRAM Width X8 08
15
Min Clock Delay for Back to
Back Random Column Address
tCCD=1CLK 01
16 Burst Lengths Supported 2,4,8 0E
17 # of banks on each DDR SDRAM device 4 bank 04
18 CAS Latency supported 2, 2.5 0C
19 CS Latency 0 CLK 01
20 WE Latency 1 CLK 02
21 DDR SDRAM Module Attributes
Registered address &
control inputs and
on-card DLL
20
22 DDR SDRAM Device Attributes: General
+/-0.2V voltage
tolerance
00
23 DDR SDRAM Cycle Time CL=2.0 7.5ns 75
24 DDR SDRAM Access from Clock CL=2.0
±0.7ns
70
25 DDR SDRAM Cycle Time CL=1.5 - 00
26 DDR SDRAM Access from Clock CL=1.5 - 00
27 Minimum Row Precharge Time (tRP) 18ns 48
28 Minimum Row Active to Row Activate delay (tRRD) 12ns 30
29 Minimum RAS to CAS Delay (tRCD) 18ns 48
30 Minimum active to Precharge time (tRAS) 42ns 2A
31 Module ROW density 256MB 40
32 Command/Address Input Setup Time 0.8ns 80
33 Command/Address Input Hold Time 0.8ns 80
34 Data Signal Input Setup Time 0.45ns 45
35 Data Signal Input Hold Time 0.45ns 45
36-61 Superset Information - 00