Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
L
L
L
D
D
D
6
6
6
4
4
4
V
V
V
6
6
6
F
F
F
5
5
5
184PIN DDR266 Unbuffered DIMM
256MB With 32Mx8 CL2.5
SERIAL PRESENCE DETECT SPECIFICATION
Serial Presence Detect
11 DIMM configuration type (non-parity, Parity, ECC) Non-ECC
DDR SDRAM Cycle Time CL=2.0 10ns A0
36-61 Superset Information
Byte No. Function Described
Standard
Specification
Vendor Part
00
12 Refresh Rate Type
24 DDR SDRAM Access from Clock CL=2.0 ± 0.75ns
- 00
0 # of Bytes Written into Serial Memory
7.8us/Self Refresh 82
75
25
128bytes 80
13 Primary DDR SDRAM Width X8
DDR SDRAM Cycle Time CL=1.5 - 00
1 Total # of Bytes of S.P.D Memory 256bytes
08
14 Error Checking DDR SDRAM Width
26 DDR SDRAM Access from Clock CL=1.5 -
08
2 Fundamental Memory Type
N/A 00
00
27
DDR SDRAM 07
3 # of Row Addresses on this Assembly 13 0D
4 # of Column Addresses on this Assembly
5 # of Module Rows on this Assembly 1 bank 01
6 Data Width of this Assembly 64bits 40
00
15
Min Clock Delay for Back to
Back Random Column Address
tCCD=1CLK 01
16 Burst Lengths Supported 2,4,8 0E
4 bank 04
18 CAS Latency supported 2, 2.5 0C
19
20 WE Latency 1 CLK
Minimum Row Precharge Time (tRP) 20ns 50
28 Minimum Row Active to Row Activate delay (tRRD) 15ns 3C
29
30 Minimum active to Precharge time (tRAS) 45ns 2D
31 Module ROW density 256MB
0.9ns 90
33 Command/Address Input Hold Time
10 0A
17 # of banks on each DDR SDRAM device
Minimum RAS to CAS Delay (tRCD) 20ns 50
7 Data Width of this Assembly 0
CS Latency 0 CLK 01
40
32 Command/Address Input Setup Time
8 VDDQ and Interface Standard of this Assembly SSTL 2.5V 04
02
21 DDR SDRAM Module Attributes
0.9ns 90
9 DDR SDRAM Cycle Time at CAS Latency=2.5 7.5ns
Registered address &
control inputs and
on-card DLL
20
34 Data Signal Input Setup Time
75
10 DDR SDRAM Access Time from Clock at CL=2.5
22 DDR SDRAM Device Attributes: General
+/-0.2V voltage
tolerance
0.5ns 50
35
± 0.75ns 75
00
23
Data Signal Input Hold Time 0.5ns 50
Transcend Information Inc.
10