Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
F
M
M
L
L
L
D
D
D
6
6
6
4
4
4
V
V
V
4
4
4
F
F
184PIN DDR400 Unbuffered DIMM
256MB With 32Mx8 CL2.5
Transcend Information Inc.
7
AC OPERATING CONDITIONS
Parameter Symbol
Input Levels (VIH/VIL) VREF+0.31/VREF-0.31 V
Min Max Unit Note
Input timing measurement reference level VREF
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC)
V
VREF + 0.31 V
Output timing measurement reference level VTT V
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC)
Output load condition See Load Circuit
VREF - 0.31 V 3
Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V
INPUT / OUTPUT CAPACITANCE
(VDD = 2.6V, VDDQ = 2.6V, TA = 25°C, f = 1MHz)
Parameter Symbol Min
1
Input Crossing Point Voltage, CK and /CK inputs
Max Unit
VIX(AC) 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2
Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)
Input capacitance (CKE0)
Input capacitance (/CS0)
V 2
Input capacitance (CK0~CK2)
Input capacitance (DM0~DM7)
Data and DQS input/output capacitance (DQ0~DQ63)
C
IN1
1. VID is the magnitude of the difference between the input level on CK and the input on /CK. Note:
CIN2
C
IN3
C
IN4
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the
DC level of the same.
CIN5
C
OUT1
-
3. These parameters should be tested at the pin on actual components and may be checked at either the pin or
the pad in simulation. The AC and DC input specifications are relative to a VREF envelope that has been
bandwidth limited 20MHz.
-
-
-
-
AC OPERATING TEST CONDITIONS (VDD=2.6, VDDQ=2.6, TA=0 to 70°C)
Parameter Value
-
57
50
Unit Note
50
25
8
Input reference voltage for Clock 0.5*VDDQ V
8
pF
pF
Input signal maximum peak swing 1.5
pF
pF
pF
pF
V
ZO=50ohm
VTT=0.5*VDDQ
RT=50ohm
C
LOAD =30pF
Output
Output Load circuit
VREF
=0.5*VDDQ