Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
L
L
L
D
D
D
6
6
6
4
4
4
V
V
V
3
3
3
F
F
F
5
5
5
184PIN DDR333 Unbuffered DIMM
256MB With 32Mx8 CL2.5
AC OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V
Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V
Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 V
1. VIH(max)=4.2V. The overshoot voltage duration is <=3ns at VDD.
2. VIL(min)=-1.5V. The undershoot voltage duration is <=3ns at VSS
3. VID is the magnitude of the difference between the input level on CK and the input on /CK
Note:
4. The Value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC
level of the same.
AC OPERATING TEST CONDITIONS (VDD=2.5, VDDQ=2.5, TA=0 to 70°C)
Parameter Value Unit Note
Input reference voltage for Clock 0.5*VDDQ V
Input signal maximum peak swing 1.5 V
Input Levels (VIH/VIL) VREF+0.31/VREF-0.31 V
Input timing measurement reference level VREF V
Output timing measurement reference level Vtt V
Output load condition See Load Circuit
ZO=50ohm
VTT=0.5*VDDQ
RT=50ohm
C
LOAD =30pF
Output
Output Load circuit
VREF
=0.5*VDDQ
INPUT / OUTPUT CAPACITANCE
(VDD = 2.5V, VDDQ = 2.5V,TA = 25°C, f = 1MHz)
Parameter Symbol Min Max Unit
Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)
Input capacitance (CKE0)
Input capacitance (/CS0)
Input capacitance (CLK0, CLK1, CLK2)
Data and DQS input/output capacitance (DQ0~DQ63)
Input capacitance (DM0~DM7)
C
IN1
CIN2
C
IN3
CIN4
C
OUT
CIN5
49
42
42
22
6
6
57
50
50
25
8
8
pF
pF
pF
pF
pF
pF
Transcend Information Inc.
7