Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
L
L
L
D
D
D
6
6
6
4
4
4
V
V
V
3
3
3
F
F
F
5
5
5
184PIN DDR333 Unbuffered DIMM
256MB With 32Mx8 CL2.5
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Max. Unit Note
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK= tCK min
DQ, DM and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle
IDD0 920 mA
Operating current - One bank Active-Read-Precharge; Burst=2;
tRC=tRC min; CL=2.5; tCK=tCK min; VIN=VREF fro DQ,DQS and DM
IDD1 1120 mA
Percharge power-down standby current; All banks idle;
power-down mode; CKE = <VIL(max); tCK= tCK min
VIN = VREF
for DQ, DQS and DM
IDD2P 24 mA
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=166MHz for DDR333
Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ, DQS and DM
IDD2F 240 mA
Active power - down standby current; one bank active; power-down mode; CKE<=
VIL (max); tCK = tCK min;
VIN = VREF for DQ, DQS and DM
IDD3P 320 mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = tCK min;
DQ, DQS and DM inputs changing twice per clock cycle; address and other control
inputs changing once per clock cycle
IDD3N 480 mA
Operating current - burst read; Burst length = 2; reads; continuous burst; One
bank active; address and control inputs changing once per clock cycle; CL=2.5 at
tCK = tCK min; 50% of data changing at every burst; lout = 0 mA
IDD4R 1,480 mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One
bank active address and control inputs changing once per clock cycle; CL=2.5 at
tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle, 50% of
input data changing at every burst
IDD4W 1,400 mA
Auto refresh current; tRC = tRFC(min) IDD5 1,560 mA
Self refresh current; CKE <= 0.2V; IDD6 24 mA
Operating current - Four bank operation;
Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7 2,800 mA
Note: 1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading capacitor.
Transcend Information Inc.
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