Datasheet

T
T
T
S
S
S
3
3
3
2
2
2
M
0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 V 2
Input capacitance (CLK0, /CLK0)
Input capacitance (DM0~DM8)
Data and DQS input/output capacitance (DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
C
IN1
CIN2
M
M
D
D
D
R
R
R
7
7
7
2
2
2
V
V
V
3
3
3
F
F
F
184PIN DDR333 Registered DIMM
256MB With 32Mx8 CL2.5
Transcend Information Inc.
7
AC OPERATING CONDITIONS
Input Levels (VIH/VIL) VREF+0.31/VREF-0.31
pF
pF
Parameter Symbol Min Max
V
Input timing measurement reference level
Unit Note
VREF V
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31
Output timing measurement reference level VTT
V 3
V
Output load condition
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC)
See Load Circuit
VREF - 0.31 V 3
Input Differential Voltage, CK and /CK inputs VID(AC) 0.7
Input/Output CAPACITANCE (VDD = 2.5V, VDDQ = 2.5V,TA = 25°C, f = 1MHz)
Parameter Symbol Min
VDDQ + 0.6 V 1
Max Unit
Input Crossing Point Voltage, CK and /CK inputs VIX(AC)
Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)
Input capacitance (CKE0, CKE1)
Input capacitance (/CS0, /CS1)
Note:
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
C
IN3
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the
DC level of the same.
C
IN4
CIN5
C
OUT1
3. These parameters should be tested at the pin on actual components and may be checked at either the pin
or the pad in simulation. The AC and DC input specifications are relative to a VREF envelope that has been
bandwidth limited 20MHz.
COUT2
9
9
9
AC OPERATING TEST CONDITIONS (VDD=2.5, VDDQ=2.5, TA=0 to 70°C)
Parameter
11
10
10
Value Unit Note
10
11
11
Input reference voltage for Clock 0.5*VDDQ
11
12
11
11
V
Input signal maximum peak swing
11
pF
pF
1.5 V
pF
pF
pF
ZO=50ohm
VTT=0.5*VDDQ
RT=50ohm
C
LOAD =30pF
Output
Output Load circuit
VREF
=0.5*VDDQ