Datasheet

8
Timing Parameters & Specifications
Speed
DDR4 2133
Unit
Parameter
Symbol
Min
Max
Average Clock Period
tCK
0.938
<1.071
ns
CK high-level width
tCH
0.48
0.52
tCK
CK low-level width
tCL
0.48
0.52
tCK
DQS_t,DQS_c to DQ skew, per group, per
access
tDQSQ
-
TBD
tCK/2
DQS_t,DQS_c to DQ Skew determin-istic,
per group, per access
tDQSQ
-
TBD
tCK/2
DQ output hold time from DQS_t,DQS_c
tQH
TBD
-
tCK/2
DQ output hold time deterministic from
DQS_t, DQS_c
tQH
TBD
-
UI
DQS_t,DQS_c to DQ Skew total, per group,
per access; DBI enabled
tDQSQ
-
TBD
UI
DQ output hold time total from DQS_t,
DQS_c; DBI enabled
tQH
TBD
-
UI
DQ to DQ offset , per group, per ac-cess
referenced to DQS_t, DQS_c
tDQSQ
TBD
TBD
UI
DQS_t, DQS_c differential READ Pre-amble
(2 clock preamble)
tRPRE
0.9
TBD
tCK
DQS_t, DQS_c differential READ Postamble
tRPST
TBD
TBD
tCK
DQS_t, DQS_c differential WRITE Preamble
tWPRE
0.9
-
tCK
DQS_t, DQS_c differential WRITE Postamble
tWPST
TBD
TBD
tCK
DQS_t and DQS_c low-impedance time
(Referenced from RL-1)
tLZ(DQS)
-360
180
ps
DQS_t and DQS_c high-impedance time
(Referenced from RL+BL/2)
tHZ(DQS)
-
180
ps
DQS_t, DQS_c differential input low pulse
width
tDQSL
0.46
0.54
tCK
DQS_t, DQS_c differential input high pulse
width
tDQSH
0.46
0.54
tCK
DQS_t, DQS_c rising edge to CK_t, CK_c
rising edge (1 clock preamble)
tDQSS
-0.27
0.27
tCK
DQS_t, DQS_c falling edge setup time to
CK_t, CK_c rising edge
tDSS
0.18
-
tCK
DQS_t, DQS_c falling edge hold time from
CK_t, CK_c rising edge
tDSH
0.18
-
tCK
Delay from start of internal write trans-action
to internal read command for different bank
group
tWTR_S
Max(2nCK, 2.5ns)
-
Delay from start of internal write trans-action
to internal read command for same bank
group
tWTR_L
Max(4nCK,7.5ns)
-
WRITE recovery time
tWR
15
-
ns
Mode Register Set command cycle time
tMRD
8
-
nCK
CAS_n to CAS_n command delay for same
bank group
tCCD_L
6
-
nCK