Datasheet

7
IDD Specification parameters Definition
( IDD values are for full operating range of Voltage and Temperature)
8GB, 1Gx72 Module(2 Rank x8)
Parameter
Symbol
DDR4 2133 CL15
Unit
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =
tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid
commands;Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD0
810
mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL
= 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS =
tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
IDD1
855
mA
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD2P
540
mA
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
IDD2Q
702
mA
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD2N
828
mA
Active power - down current; All banks open; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD3P
792
mA
Active standby current; All banks open; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD3N
1134
mA
Operating burst read current; All banks open, Continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W
IDD4R
1620
mA
Operating burst write current; All banks open, Continuous burst writes; BL
= 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R
IDD4W
1710
mA
Burst refresh current; tCK = tCK(IDD); Refresh command at every
tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD5
1980
mA
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING
IDD6
360
mA
Operating bank interleave read current; All bank interleaving reads,
IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =
tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE
during DESELECTs; Data pattern is same as IDD4R;
IDD7
1935
mA
Note:
Module IDD was calculated on the specific brand DRAM(2Xnm) component IDD and can be differently
measured according to DQ loading capacitor.