Datasheet

11
78-116
Reserved
-
00
117
Fine Offset for Minimum CAS to CAS Delay Time
(tCCD_Lmin), same bank group
-
EC
118
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Lmin), same bank group
-
B5
119
Fine Offset for Minimum Activate to Activate Delay
Time (tRRD_Smin), different bank group
-
CE
120
Fine Offset for Minimum Active to Active/Refresh
Delay Time (tRCmin)
-
00
121
Fine Offset for Minimum Row Precharge Delay Time
(tRPmin)
-
00
122
Fine Offset for Minimum RAS to CAS Delay Time
(tRCDmin)
-
00
123
Fine Offset for Minimum CAS Latency Time (tAAmin)
-
00
124
Fine Offset for SDRAM Maximum Cycle Time
(tCKAVGmax)
-
00
125
Fine Offset for SDRAM Minimum Cycle Time
(tCKAVGmin)
-
C2
126-127
Cyclical Redundancy Code
-
-
128
Raw Card Extension, Module Nominal Height
30mm
0F
129
Module Maximum Thickness
Planar Double Sides
11
130
Reference Raw Card Used
Revision 0, Raw card G
06
131
Address Mapping from Edge Connector to DRAM
Mirrored
01
132-253
Reserved
-
00
254-255
Cyclical Redundancy Code (CRC)
-
-
256-319
Reserved
-
00
320-321
Module Manufacturer ID Code
Transcend
01,4F
322
Module Manufacturing Location
Taipei
54
323-324
Module Manufacturing Date
-
00
325-328
Module Serial Number
-
00
329-348
Module Part Number
TS1GSH72V1H
54
53
31
47
53
48
37
32
56
31
48
20
20
20
20
20
20
20
20
20
349
Module Revision Code
-
00
350-351
DRAM Manufacturer ID Code
By Manufacturer
Variable
352
DRAM Stepping
-
00
353-381
Manufacturer Specific Data
By Manufacturer
Variable
382-383
Reserved
-
00
384-551
End User Programmable
-
-