Datasheet

1
260Pin DDR4 2133 ECC SO-DIMM
8GB Based on 512Mx8
TS1GSH72V1H
Description
DDR4 ECC SO-DIMMs are high-speed, low power
memory modules that use 512Mx8bits DDR4 SDRAM in
FBGA package and a 4K-bit serial EEPROM on a 260-pin
printed circuit board. DDR4 ECC SO-DIMMs are Dual
In-Line memory modules and are intended for mounting
into 260-pin edge connector sockets.
The synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges of DQS. The large range of
operation frequencies and programmable latencies allow
the same device to be useful for a variety of high
bandwidth and high performance memory system
applications.
Features
 RoHS compliant
 JEDEC standard 1.2V ± 0.06V power supply
 VDDQ=1.2V ± 0.06V
 Clock Freq: 1067MHZ for 2133Mb/s/Pin.
 Programmable CAS Latency: 10,11,12,13,14,15,16
 Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
 Programmable /CAS Write Latency (CWL)
= 11, 14(DDR4-2133)
 8 bit pre-fetch
 Burst Length: 4, 8
 Bi-directional Differential Data-Strobe
 On Die Termination with ODT pin
 Serial presence detect with EEPROM
 On DIMM Thermal Sensor
 Asynchronous reset
Pin Identification
Symbol
Function
A0–A14
SDRAM address bus
BA0, BA1
SDRAM bank select
BG0, BG1
SDRAM bank group select
RAS_n
SDRAM row address strobe
CAS_n
SDRAM column address strobe
WE_n
SDRAM write enable
CS0_n, CS1_n
DIMM Rank Select Lines
CKE0, CKE1
SDRAM clock enable lines
ODT0, ODT1
SDRAM on-die termination control
lines
ACT_n
SDRAM activate
DQ0–DQ63
DIMM memory data bus
CB0–CB7
DIMM ECC check bits
DM_n/DBI_n/
Input data mask and data bus
inversion
DQS0_t–DQS8_t
SDRAM data strobes
(positive line of differential pair)
DQS0_c–DQS8_c
SDRAM data strobes
(negative line of differential pair)
CK0_t, CK1_t
SDRAM clocks
(positive line of differential pair)
CK0_c, CK1_c
SDRAM clocks
(negative line of differential pair)
PARITY
SDRAM parity input
VDD
SDRAM I/O and core power supply
VREFCA
SDRAM command/address
reference supply
VSS
Power supply return (ground)
VDDSPD
Serial SPD EEPROM positive
power supply
SCL
I
2
C serial bus clock for EEPROM
SDA
I
2
C serial bus data line for
EEPROM
SA0–SA2
I
2
C slave address select for
EEPROM
ALERT_n
SDRAM ALERT_n
VPP
SDRAM Supply
RESET_n
Set DRAMs to a Known State
EVENT_n
SPD signals a thermal event has
occurred
VTT
SDRAM I/O termination supply
RFU
Reserved for future use
NC
No Connection
NF
No function