Datasheet

T
T
T
S
S
S
1
1
1
6
6
6
M
M
M
L
L
L
S
S
S
7
7
7
2
2
2
V
V
V
8
8
8
D
D
D
128MB 168Pin PC100 CL3 ECC
SDRAM DIMM With 16Mx8 3.3VOLT

Transcend Information Inc.



AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, TA = 0 to 70
°
C)
Parameter Value Unit
AC Input levels (V
IH
/V
IL
) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf=1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2

Output
(Fig. 1) DC Output Load Circuit
3.3V
1200 Ohm
50pF
870 Ohm
V
OH
(DC)=2.4V, I
OH
=-2mA
V
OL
(DC)=0.4V, I
OL
=2mA

Output
(Fig. 2) AC Output Load Circuit
Vtt=1.4V
50 Ohm
50pF
Z0=50 Ohm
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter Symbol Value Unit Note
Row active to row active delay t
RRD
(min) 20 ns 1
/RAS to /CAS delay t
RCD
(min) 20 ns 1
Row precharge time t
RP
(min) 20 ns 1
t
RAS
(min) 50 ns 1
Row active time
t
RAS
(max) 100 us
Row cycle time t
RC
(min) 70 ns 1
Last data in to new col. address delay t
CDL
(min) 1 CLK 2
Last data in to row precharge t
RDL
(min) 2 CLK 2
Last data in to burst stop t
BDL
(min) 1 CLK 2
Col. address to col. address delay t
CCD
(min) 1 CLK 3
CAS latency=3 2
Number of valid
output data
- -
ea 4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.