Datasheet
T
T
T
S
S
S
1
1
1
6
6
6
M
G
M
M
L
L
L
D
D
D
6
6
6
4
4
4
V
V
V
6
6
6
G
G
184PIN DDR266 Unbuffered DIMM
128MB With 16Mx16 CL2.5
Transcend Information Inc.
7
AC OPERATING CONDITIONS
Input Levels(VIH/VIL) VREF+0.31/VREF-0.31
Parameter Symbol Min
V
Max
Unit Note
Input timing measurement reference level VREF V
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31
Output timing measurement reference level Vtt
V 3
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC)
Output load condition See Load Circuit
VREF - 0.31 V 3
Input/Output CAPACITANCE
(VDD = 2.5V, VDDQ = 2.5V,TA = 25°C, f = 1MHz)
Input Differential Voltage, CK and /CK inputs VID(AC)
Parameter Symbol Min
0.7 VDDQ + 0.6 V 1
Max Unit
Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)
Input Crossing Point Voltage, CK and /CK inputs VIX(AC)
Input capacitance (CKE0)
Input capacitance (/CS0)
Input capacitance (CK0, CK1)
0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 V
Input capacitance (DM0~DM7)
Data and DQS input/output capacitance (DQ0~DQ63)
C
IN1
2
Note:
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
CIN2
C
IN3
C
IN4
CIN5
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the
DC level of the same.
C
OUT1
29
29
3. These parameters should be tested at the pin on actual components and may be checked at either the pin or
the pad in simulation. The AC and DC input specifications are relative to a VREF envelope that has been
bandwidth limited 20MHz.
26
30
8
AC OPERATING TEST CONDITIONS
(VDD=2.5, VDDQ=2.5, TA=0 to 70°C)
Parameter
8
34
34
30
Value Unit Note
9
Input reference voltage for Clock 0.5*VDDQ
pF
pF
pF
V
Input signal maximum peak swing
pF
pF
pF
1.5 V
ZO=50ohm
VTT=0.5*VDDQ
RT=50ohm
C
LOAD
=30pF
Output
Output Load circuit
VREF
=0.5*VDDQ
32
9