Datasheet

T
T
T
S
S
S
1
1
1
6
6
6
M
M
M
L
L
L
D
D
D
6
6
6
4
4
4
V
V
V
6
6
6
D
D
D
5
5
5
184PIN DDR266 Unbuffered DIMM
128MB With 16Mx8 CL2.5
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, VDD=2.7V, TA = 10 °C)
Parameter Symbol Max. Unit Note
Operating current - One bank Active-Precharge; tRC=tRCmin;
tCK=133MHZ for DDR266
DQ, DM and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle
IDD0 760 mA
Operating current - One bank operation; One bank open, Burst=4; Reads
- Refer to the following page for detailed test condition.
IDD1 960 mA
Percharge power-down standby current; All banks idle; power –down mode;
CKE = <VIL(max); tCK=133MHZ for DDR266, VIN = VREF for DQ,DQS and DM
IDD2P 24 mA
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=133MHZ for DDR266, Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ,DQS and DM
IDD2F 176 mA
Precharge Quiet Standby current; CS#>=VIH (min); All banks idle;
CKE>=VIH(min); tCK=133MHZ for DDR266; Address and other control inputs
stable with keeping >=VIH(min) or =< VIL(max); VIN=VREF for DQ,DQS and DM
IDD2Q 120
Active power - down standby current; one bank active; power-down mode;
CKE<= VIL (max); tCK=133MHZ for DDR266; VIN = VREF for DQ,DQS and DM
IDD3P 280 mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK=133MHZ for DDR266;
DQ, DQS and DM inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
IDD3N 440 mA
Operating current - burst read; Burst length = 2; reads; continuous burst;
One bank active; address and control inputs changing once per clock cycle;
50% of data changing at every burst; lout = 0 mA
IDD4R 1136 mA
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
CL=2.5 at tCK=133MHZ for DDR266; DQ, DM and DQS inputs changing twice per
clock cycle, 50% of input data changing at every burst
IDD4W 1040 mA
Auto refresh current; tRC = tRFC(min),
10*tCK for DDR266at 133Mhz; distributed refresh
IDD5 1480 mA
Self refresh current; CKE <= 0.2V; External clock should be on;
tCK=133MHZ for DDR266;
IDD6 16 mA
Operating current - Four bank operation; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7 2400 mA
Note:
1. Module IDD was calculated on the basis of component IDD and can be differently measured according to
DQ loading capacitor.
Transcend Information Inc.
6