Datasheet

T
T
T
S
S
S
1
1
1
6
6
6
M
M
M
E
E
E
D
D
D
3
3
3
2
2
2
6
6
6
0
0
0
V
V
V
64MB 72 PIN EDO
DRAM SIMM With 16Mx4 3.3VOLT
/RAS pulse width (Hyper page cycle) tRASP 60 200K ns
/W to /RAS precharge time (C-B-R refresh) tWRP 10 ns
/W to /RAS hold time (C-B-R refresh) tWRH 10 ns
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only or
/CAS-before-/RAS refresh cycles before proper device operation is achieved.
2. Input voltage levels are V
IH/VIL. VIH(min) and VIL(max) are reference levels for measuring
timing of input signals. Transition times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the t
RCD(max) limit insures that tRAC(max) can be met. tRCD(max) is
specified as a reference point only. If t
RCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by t
CAC.
5. Assumes that tRCD≧tRCD(max).
6. This parameter defines the time at which the output achieves the open circuit condition
and is not referenced to V
OH or VOL..
7. t
WCS is non-restrictive operating parameter. It is included in the data sheet as electrical
characteristics only. If tWCS≧tWCS(min), the cycle is an early write cycle and the data out
pin will remain high impedance for the duration of the cycle.
8. Either t
RCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to the /CAS leading edge in early write cycle.
10. Operation within the t
RAD(max) limit insures that tRAC(max) can be met. tRAD(max) is
specified as reference point only. If t
RAD is greater than the specified tRAD(max) limit, then
access time is controlled by t
AA.
Transcend Information Inc.
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