Datasheet

T
T
T
S
S
S
8
8
8
G
G
G
S
S
S
S
S
S
D
D
D
2
2
2
5
5
5
H
H
H
-
-
-
M
M
M
T
T
T
S
S
S
1
1
1
6
6
6
G
G
G
S
S
S
S
S
S
D
D
D
2
2
2
5
5
5
H
H
H
-
-
-
M
M
M
T
T
T
S
S
S
3
3
3
2
2
2
G
G
G
S
S
S
S
S
S
D
D
D
2
2
2
5
5
5
H
H
H
-
-
-
M
M
M
T
T
T
S
S
S
6
6
6
4
4
4
G
G
G
S
S
S
S
S
S
D
D
D
2
2
2
5
5
5
H
H
H
-
-
-
M
M
M
2.5” Half-Slim
Solid State Disk
Transcend Information Inc.
Preliminary V0.7
11
the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword
times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting
the release of COMWAKE to receive the first ALIGN
P
. This ensures interoperability with multi-generational and
synchronous designs. If no ALIGN
P
is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the
power-on sequence – repeating indefinitely until told to stop by the Application layer. 6. Device locks – the device locks to
the ALIGN sequence and, when ready, sends SYNC
P
indicating it is ready to start normal operation.
6. Upon receipt of three back-to-back non-ALIGN
P
primitives, the communication link is established and normal operation
may begin.
Power on sequence timing diagram
The following timing diagrams and descriptions are provided for clarity and are informative.
Figure 7 : power on sequence
Description:
1. Host/device power-off - Host and device power-off.
2. Power is applied - Host side signal conditioning pulls TX and RX pairs to neutral state (common mode voltage).
3. Host issues COMRESET