Datasheet

T
T
T
r
r
r
a
a
a
n
n
n
s
s
s
c
c
c
e
e
e
n
n
n
d
d
d
4
4
4
0
0
0
-
-
-
P
P
P
i
i
i
n
n
n
I
I
I
D
D
D
E
E
E
F
F
F
l
l
l
a
a
a
s
s
s
h
h
h
M
M
M
o
o
o
d
d
d
u
u
u
l
l
l
e
e
e
T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
~
~
~
1
1
1
6
6
6
G
G
G
D
D
D
O
O
O
M
M
M
4
4
4
0
0
0
V
V
V
-
-
-
S
S
S
Transcend Information Inc.
Ver 1.3
9
True IDE Multiword DMA Mode Read/Write Timing Diagram
Figure 2: True IDE Multiword DMA Mode Read/Write Timing Diagram
Notes:
(1) If the Card cannot sustain continuous, minimum cycle time DMA transfers, it may negate DMARQ within the
time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert
the signal at a later time to continue the DMA operation.
(2) This signal may be negated by the host to suspend the DMA transfer in progress.