Datasheet

T
T
T
r
r
r
a
a
a
n
n
n
s
s
s
c
c
c
e
e
e
n
n
n
d
d
d
4
4
4
0
0
0
-
-
-
P
P
P
i
i
i
n
n
n
I
I
I
D
D
D
E
E
E
F
F
F
l
l
l
a
a
a
s
s
s
h
h
h
M
M
M
o
o
o
d
d
d
u
u
u
l
l
l
e
e
e
T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
~
~
~
1
1
1
6
6
6
G
G
G
D
D
D
O
O
O
M
M
M
4
4
4
0
0
0
V
V
V
-
-
-
S
S
S
Transcend Information Inc.
Ver 1.3
8
True IDE Multiword DMA Mode Read/Write Timing Specification
Item
Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
t
0
Cycle time (min)
1
480 150 120 100 80
t
D
-IORD / -IOWR asserted width(min)
1
215 80 70 65 55
t
E
-IORD data access (max) 150 60 50 50 45
t
F
-IORD data hold (min) 5 5 5 5 5
t
G
-IORD/-IOWR data setup (min) 100 30 20 15 10
t
H
-IOWR data hold (min) 20 15 10 5 5
t
I
DMACK to –IORD/-IOWR setup (min) 0 0 0 0 0
t
J
-IORD / -IOWR to -DMACK hold (min) 20 5 5 5 5
t
KR
-IORD negated width (min)
1
50 50 25 25 20
t
KW
-IOWR negated width (min)
1
215 50 25 25 20
t
LR
-IORD to DMARQ delay (max) 120 40 35 35 35
t
LW
-IOWR to DMARQ delay (max) 40 40 35 35 35
t
M
CS(1:0) valid to –IORD / -IOWR 50 30 25 10 5
t
N
CS(1:0) hold 15 10 10 10 10
t
Z
-DMACK 20 25 25 25 25
Notes:
(1) t
0
is the minimum total cycle time and t
D
is the minimum command active time, while t
KR
and t
KW
are the
minimum command recovery time or command inactive time for input and output cycles respectively. The
actual cycle time equals the sum of the actual command active time and the actual command inactive
time. The three timing requirements of t
0
, t
D
, t
KR
, and t
KW
shall be met. The minimum total cycle time
requirement is greater than the sum of t
D
and t
KR
or t
KW
.for input and output cycles respectively. This
means a host implementation can lengthen either or both of t
D
and either of t
KR
, and t
KW
as needed to
ensure that t
0
is equal to or greater than the value reported in the device’s identify device data.