Datasheet

T
T
T
r
r
r
a
a
a
n
n
n
s
s
s
c
c
c
e
e
e
n
n
n
d
d
d
4
4
4
0
0
0
-
-
-
P
P
P
i
i
i
n
n
n
I
I
I
D
D
D
E
E
E
F
F
F
l
l
l
a
a
a
s
s
s
h
h
h
M
M
M
o
o
o
d
d
d
u
u
u
l
l
l
e
e
e
T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
~
~
~
1
1
1
6
6
6
G
G
G
D
D
D
O
O
O
M
M
M
4
4
4
0
0
0
V
V
V
-
-
-
S
S
S
Transcend Information Inc.
Ver 1.3
22
(p) In True IDE mode, the host shall not assert -IORD, -CS0, -CS1, nor A[02:00] until at least t
ACK
after
negating DMACK.
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.