Datasheet

T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
S
S
S
D
D
D
6
6
6
4
4
4
V
V
V
6
6
6
A
A
A
200PIN DDR266 Unbuffered SO-DIMM
1GB With 64Mx8 CL2.5
SIMPLIFIED TRUTH TABLE (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
COMMAND
Exit L H
All Banks
H H H
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
CKEn-1 CKEn /CS
L H H
6. During burst write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued
after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in is masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation (NOP)" in DDR SDRAM.
/RAS /CAS /WE BA 0,1
H 3
X
H
4
X H
Exit
L
A 10 /AP A 0 ~A 9, A 11, A 12 Note
Auto Precharge Disable
Write &
Column Address
5
Active Power Down
H X
H
Register
Extended
H
H X L
Entry H L
X X
Mode Register Set
H X L
X X X
H L L V
H X X X
L L L
3
Bank Active & Row Addr.
L
Column
Address
X
L
OP CODE 1,2
H X L
4
(A
0 ~A 9 )
V V V
Register Mode Register Set H X
L H H V
Auto Precharge Enable
L V V
DM
L L L
Row Address
V
H X X
L OP CODE 1,2
H
4, 6
Burst Stop H
Exit L H X X X X
8
H X X
No Operation Command
H X
Auto Refresh
Refresh
H
H LL
X L
3
Auto Precharge Disable
H X
X 7
Entry
H
Down Mode
L
Entry
Self
Refresh
L H L H
Bank Selection
Precharge H X
H X
L
H H H
L
L
V
Column
L L H
X X
X
9
L H X
Read &
Column Address
H H L
Precharge Power
3
Auto Precharge Enable
X
L
4. BA0 ~ BA1: Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
4
Address
(A 0 ~A 9 )
V L
L
Note: 1. OP Code: Operand Code. A0 ~ A12 & BA0 ~ BA1: Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM. The automatically precharge without row precharge command is meant by
"Auto". Auto/self refresh can be issued only at all banks precharge state.
X 9
X
Transcend Information Inc.
10