Datasheet

T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
S
S
S
D
D
D
6
6
6
4
4
4
V
V
V
4
4
4
A
A
A
200PIN DDR400 Unbuffered SO-DIMM
1GB With 64Mx8 CL3
Exit self refresh to bank active command tXSA 7.5 ns 5
Exit self refresh to read command tXSR 200 Cycle
Refresh interval time tREF - 7.8 us 1
Clock half period
tHP tCLmin or
tCHmin
ns
Data hold skew factor tQHS 0.5 ns
DQS write post amble time tWPST 0.4 0.6 tck 3
Note: 1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown
(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a
previous write was in progress, DQS could be High at this time, depending on tDQSS.
3. The Maximum limit for this parameter is not a device limit. The device will operate with a great value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
4. For registered DIMMs, tCL and tCH are >= 45% of the period including both the half period jitter (tJIT(HP) ) of
the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
5. A write command can be applied with tRCD satisfied after this command.
Transcend Information Inc.
9